src/mainboard/ibm/e326/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <stdlib.h>
   9 #include <pc80/mc146818rtc.h>
  10 #include <console/console.h>
  11
  12 #include <cpu/amd/model_fxx_rev.h>
  13 #include "northbridge/amd/amdk8/incoherent_ht.c"
  14 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  15 #include "northbridge/amd/amdk8/raminit.h"
  16 #include "cpu/amd/model_fxx/apic_timer.c"
  17 #include "lib/delay.c"
  18
  19 #include "cpu/x86/lapic/boot_cpu.c"
  20 #include "northbridge/amd/amdk8/reset_test.c"
  21 #include "northbridge/amd/amdk8/debug.c"
  22 #include "superio/nsc/pc87366/pc87366_early_serial.c"
  23
  24 #include "cpu/x86/mtrr/earlymtrr.c"
  25 #include "cpu/x86/bist.h"
  26
  27 #include "northbridge/amd/amdk8/setup_resource_map.c"
  28
  29 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
  30
  31 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  32 #include <spd.h>
  33
  34 static void memreset_setup(void)
  35 {
  36         if (is_cpu_pre_c0()) {
  37                 /* Set the memreset low */
  38                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
  39                 /* Ensure the BIOS has control of the memory lines */
  40                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  41         } else {
  42                 /* Ensure the CPU has controll of the memory lines */
  43                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
  44         }
  45 }
  46
  47 static void memreset(int controllers, const struct mem_controller *ctrl)
  48 {
  49         if (is_cpu_pre_c0()) {
  50                 udelay(800);
  51                 /* Set memreset_high */
  52                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
  53                 udelay(90);
  54         }
  55 }
  56
  57 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  58 {
  59         /* nothing to do */
  60 }
  61
  62 static inline int spd_read_byte(unsigned device, unsigned address)
  63 {
  64         return smbus_read_byte(device, address);
  65 }
  66
  67
  68 #include "northbridge/amd/amdk8/raminit.c"
  69 #include "resourcemap.c"
  70 #include "northbridge/amd/amdk8/coherent_ht.c"
  71 #include "lib/generic_sdram.c"
  72
  73 #include "cpu/amd/dualcore/dualcore.c"
  74
  75 #include "cpu/amd/car/post_cache_as_ram.c"
  76
  77 #include "cpu/amd/model_fxx/init_cpus.c"
  78
  79 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  80 #include "northbridge/amd/amdk8/early_ht.c"
  81
  82 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  83 {
  84         static const struct mem_controller cpu[] = {
  85                 {
  86                         .node_id = 0,
  87                         .f0 = PCI_DEV(0, 0x18, 0),
  88                         .f1 = PCI_DEV(0, 0x18, 1),
  89                         .f2 = PCI_DEV(0, 0x18, 2),
  90                         .f3 = PCI_DEV(0, 0x18, 3),
  91                         .channel0 = { DIMM0, DIMM2, 0, 0 },
  92                         .channel1 = { DIMM1, DIMM3, 0, 0 },
  93                 },
  94 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  95                 {
  96                         .node_id = 1,
  97                         .f0 = PCI_DEV(0, 0x19, 0),
  98                         .f1 = PCI_DEV(0, 0x19, 1),
  99                         .f2 = PCI_DEV(0, 0x19, 2),
 100                         .f3 = PCI_DEV(0, 0x19, 3),
 101                         .channel0 = { DIMM4, DIMM6, 0, 0 },
 102                         .channel1 = { DIMM5, DIMM7, 0, 0 },
 103                 },
 104 #endif
 105         };
 106
 107         int needs_reset;
 108
 109         if (!cpu_init_detectedx && boot_cpu()) {
 110                 /* Nothing special needs to be done to find bus 0 */
 111                 /* Allow the HT devices to be found */
 112
 113                 enumerate_ht_chain();
 114
 115                 amd8111_enable_rom();
 116         }
 117
 118         if (bist == 0) {
 119                 init_cpus(cpu_init_detectedx);
 120         }
 121
 122         pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 123         uart_init();
 124         console_init();
 125
 126         /* Halt if there was a built in self test failure */
 127         report_bist_failure(bist);
 128
 129         setup_ibm_e326_resource_map();
 130
 131         needs_reset = setup_coherent_ht_domain();
 132
 133 #if CONFIG_LOGICAL_CPUS==1
 134         // It is said that we should start core1 after all core0 launched
 135         start_other_cores();
 136 #endif
 137         // automatically set that for you, but you might meet tight space
 138         needs_reset |= ht_setup_chains_x();
 139
 140         if (needs_reset) {
 141                 print_info("ht reset -\n");
 142                 soft_reset();
 143         }
 144
 145         enable_smbus();
 146
 147         memreset_setup();
 148         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 149
 150         post_cache_as_ram();
 151
 152 }
 153