1 uses CONFIG_GENERATE_MP_TABLE
2 uses CONFIG_GENERATE_PIRQ_TABLE
3 uses CONFIG_USE_FALLBACK_IMAGE
4 uses CONFIG_HAVE_FALLBACK_BOOT
5 uses CONFIG_HAVE_HARD_RESET
6 uses CONFIG_IRQ_SLOT_COUNT
7 uses CONFIG_HAVE_OPTION_TABLE
9 uses CONFIG_MAX_PHYSICAL_CPUS
12 uses CONFIG_FALLBACK_SIZE
14 uses CONFIG_ROM_SECTION_SIZE
15 uses CONFIG_ROM_IMAGE_SIZE
16 uses CONFIG_ROM_SECTION_SIZE
17 uses CONFIG_ROM_SECTION_OFFSET
18 uses CONFIG_ROM_PAYLOAD
19 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
20 uses CONFIG_PRECOMPRESSED_PAYLOAD
22 uses CONFIG_XIP_ROM_SIZE
23 uses CONFIG_XIP_ROM_BASE
24 uses CONFIG_STACK_SIZE
26 uses CONFIG_USE_OPTION_TABLE
27 uses CONFIG_LB_CKS_RANGE_START
28 uses CONFIG_LB_CKS_RANGE_END
29 uses CONFIG_LB_CKS_LOC
30 uses CONFIG_MAINBOARD_PART_NUMBER
31 uses CONFIG_MAINBOARD_VENDOR
33 uses COREBOOT_EXTRA_VERSION
35 uses CONFIG_TTYS0_BAUD
36 uses CONFIG_TTYS0_BASE
38 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
39 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
40 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
41 uses CONFIG_CONSOLE_SERIAL8250
42 uses CONFIG_CROSS_COMPILE
46 uses CONFIG_CONSOLE_VGA
47 uses CONFIG_PCI_ROM_RUN
48 uses CONFIG_USE_DCACHE_RAM
49 uses CONFIG_DCACHE_RAM_BASE
50 uses CONFIG_DCACHE_RAM_SIZE
52 uses CONFIG_USE_PRINTK_IN_CAR
60 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
62 default CONFIG_ROM_SIZE=524288
65 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
67 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
70 ## Build code for the fallback boot
72 default CONFIG_HAVE_FALLBACK_BOOT=1
75 ## Build code to reset the motherboard from coreboot
77 default CONFIG_HAVE_HARD_RESET=1
80 ## Build code to export a programmable irq routing table
82 default CONFIG_GENERATE_PIRQ_TABLE=1
83 default CONFIG_IRQ_SLOT_COUNT=12
86 ## Build code to export an x86 MP table
87 ## Useful for specifying IRQ routing values
89 default CONFIG_GENERATE_MP_TABLE=1
92 ## Build code to export a CMOS option table
94 default CONFIG_HAVE_OPTION_TABLE=1
97 ## Move the default coreboot cmos range off of AMD RTC registers
99 default CONFIG_LB_CKS_RANGE_START=49
100 default CONFIG_LB_CKS_RANGE_END=122
101 default CONFIG_LB_CKS_LOC=123
104 ## Build code for SMP support
105 ## Only worry about 2 micro processors
108 default CONFIG_MAX_CPUS=2
109 default CONFIG_MAX_PHYSICAL_CPUS=2
112 ## Build code to setup a generic IOAPIC
114 default CONFIG_IOAPIC=1
117 default CONFIG_CONSOLE_VGA=1
118 default CONFIG_PCI_ROM_RUN=1
121 ## enable CACHE_AS_RAM specifics
123 default CONFIG_USE_DCACHE_RAM=1
124 default CONFIG_DCACHE_RAM_BASE=0xcf000
125 default CONFIG_DCACHE_RAM_SIZE=0x1000
126 default CONFIG_USE_INIT=0
129 ## Clean up the motherboard id strings
131 default CONFIG_MAINBOARD_PART_NUMBER="E326"
132 default CONFIG_MAINBOARD_VENDOR="IBM"
133 #default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
134 #default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
137 ### coreboot layout values
140 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
141 default CONFIG_ROM_IMAGE_SIZE = 65536
144 ## Use a small 8K stack
146 default CONFIG_STACK_SIZE=0x2000
149 ## Use a small 16K heap
151 default CONFIG_HEAP_SIZE=0x8000
154 ## Only use the option table in a normal image
156 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
159 ## Coreboot C code runs at this location in RAM
161 default CONFIG_RAMBASE=0x00004000
164 ## Load the payload from the ROM
166 default CONFIG_ROM_PAYLOAD = 1
169 ### Defaults of options that you may want to override in the target config file
173 ## The default compiler
175 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
178 default CONFIG_USE_PRINTK_IN_CAR=1
181 ## The Serial Console
184 # To Enable the Serial Console
185 default CONFIG_CONSOLE_SERIAL8250=1
187 ## Select the serial console baud rate
188 default CONFIG_TTYS0_BAUD=115200
189 #default CONFIG_TTYS0_BAUD=57600
190 #default CONFIG_TTYS0_BAUD=38400
191 #default CONFIG_TTYS0_BAUD=19200
192 #default CONFIG_TTYS0_BAUD=9600
193 #default CONFIG_TTYS0_BAUD=4800
194 #default CONFIG_TTYS0_BAUD=2400
195 #default CONFIG_TTYS0_BAUD=1200
197 # Select the serial console base port
198 default CONFIG_TTYS0_BASE=0x3f8
200 # Select the serial protocol
201 # This defaults to 8 data bits, 1 stop bit, and no parity
202 default CONFIG_TTYS0_LCS=0x3
205 ### Select the coreboot loglevel
207 ## EMERG 1 system is unusable
208 ## ALERT 2 action must be taken immediately
209 ## CRIT 3 critical conditions
210 ## ERR 4 error conditions
211 ## WARNING 5 warning conditions
212 ## NOTICE 6 normal but significant condition
213 ## INFO 7 informational
214 ## CONFIG_DEBUG 8 debug-level messages
215 ## SPEW 9 Way too many details
217 ## Request this level of debugging output
218 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
219 ## At a maximum only compile in this level of debugging
220 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
223 ## Select power on after power fail setting
224 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"