src/mainboard/ibm/e325/romstage.c

   1
   2 #include <stdint.h>
   3 #include <string.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <stdlib.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "console/console.c"
  14 #include "lib/ramtest.c"
  15
  16 #include <cpu/amd/model_fxx_rev.h>
  17 #include "northbridge/amd/amdk8/incoherent_ht.c"
  18 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  19 #include "northbridge/amd/amdk8/raminit.h"
  20 #include "cpu/amd/model_fxx/apic_timer.c"
  21 #include "lib/delay.c"
  22
  23 #include "cpu/x86/lapic/boot_cpu.c"
  24 #include "northbridge/amd/amdk8/reset_test.c"
  25 #include "northbridge/amd/amdk8/debug.c"
  26 #include "superio/nsc/pc87366/pc87366_early_serial.c"
  27
  28 #include "cpu/x86/mtrr/earlymtrr.c"
  29 #include "cpu/x86/bist.h"
  30
  31 #include "northbridge/amd/amdk8/setup_resource_map.c"
  32
  33 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
  34
  35 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  36
  37 static void memreset_setup(void)
  38 {
  39         if (is_cpu_pre_c0()) {
  40                 /* Set the memreset low */
  41                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
  42                 /* Ensure the BIOS has control of the memory lines */
  43                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  44         } else {
  45                 /* Ensure the CPU has controll of the memory lines */
  46                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
  47         }
  48 }
  49
  50 static void memreset(int controllers, const struct mem_controller *ctrl)
  51 {
  52         if (is_cpu_pre_c0()) {
  53                 udelay(800);
  54                 /* Set memreset_high */
  55                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
  56                 udelay(90);
  57         }
  58 }
  59
  60 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  61 {
  62         /* nothing to do */
  63 }
  64
  65 static inline int spd_read_byte(unsigned device, unsigned address)
  66 {
  67         return smbus_read_byte(device, address);
  68 }
  69
  70 #define QRANK_DIMM_SUPPORT 1
  71
  72 #include "northbridge/amd/amdk8/raminit.c"
  73 #include "resourcemap.c"
  74 #include "northbridge/amd/amdk8/coherent_ht.c"
  75 #include "lib/generic_sdram.c"
  76
  77 #if CONFIG_LOGICAL_CPUS==1
  78 #define SET_NB_CFG_54 1
  79 #endif
  80 #include "cpu/amd/dualcore/dualcore.c"
  81
  82 #define FIRST_CPU  1
  83 #define SECOND_CPU 1
  84 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
  85
  86
  87
  88 #include "cpu/amd/car/post_cache_as_ram.c"
  89
  90 #include "cpu/amd/model_fxx/init_cpus.c"
  91
  92 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  93 #include "northbridge/amd/amdk8/early_ht.c"
  94
  95 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  96 {
  97         static const struct mem_controller cpu[] = {
  98                 {
  99                         .node_id = 0,
 100                         .f0 = PCI_DEV(0, 0x18, 0),
 101                         .f1 = PCI_DEV(0, 0x18, 1),
 102                         .f2 = PCI_DEV(0, 0x18, 2),
 103                         .f3 = PCI_DEV(0, 0x18, 3),
 104                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 105                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 106                 },
 107 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 108                 {
 109                         .node_id = 1,
 110                         .f0 = PCI_DEV(0, 0x19, 0),
 111                         .f1 = PCI_DEV(0, 0x19, 1),
 112                         .f2 = PCI_DEV(0, 0x19, 2),
 113                         .f3 = PCI_DEV(0, 0x19, 3),
 114                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 115                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 116                 },
 117 #endif
 118         };
 119
 120         int needs_reset;
 121
 122         if (!cpu_init_detectedx && boot_cpu()) {
 123                 /* Nothing special needs to be done to find bus 0 */
 124                 /* Allow the HT devices to be found */
 125
 126                 enumerate_ht_chain();
 127
 128                 amd8111_enable_rom();
 129         }
 130
 131         if (bist == 0) {
 132                 init_cpus(cpu_init_detectedx);
 133         }
 134
 135         pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 136         uart_init();
 137         console_init();
 138
 139         /* Halt if there was a built in self test failure */
 140         report_bist_failure(bist);
 141
 142         setup_ibm_e325_resource_map();
 143
 144         needs_reset = setup_coherent_ht_domain();
 145
 146 #if CONFIG_LOGICAL_CPUS==1
 147         // It is said that we should start core1 after all core0 launched
 148         start_other_cores();
 149 #endif
 150         // automatically set that for you, but you might meet tight space
 151         needs_reset |= ht_setup_chains_x();
 152
 153         if (needs_reset) {
 154                 print_info("ht reset -\n");
 155                 soft_reset();
 156         }
 157
 158         enable_smbus();
 159
 160         memreset_setup();
 161         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 162
 163         post_cache_as_ram();
 164
 165 }
 166