src/mainboard/ibm/e325/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <stdlib.h>
   9 #include <pc80/mc146818rtc.h>
  10 #include <console/console.h>
  11 #include <cpu/amd/model_fxx_rev.h>
  12 #include "northbridge/amd/amdk8/incoherent_ht.c"
  13 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  14 #include "northbridge/amd/amdk8/raminit.h"
  15 #include "cpu/amd/model_fxx/apic_timer.c"
  16 #include "lib/delay.c"
  17 #include "cpu/x86/lapic/boot_cpu.c"
  18 #include "northbridge/amd/amdk8/reset_test.c"
  19 #include "northbridge/amd/amdk8/debug.c"
  20 #include "superio/nsc/pc87366/pc87366_early_serial.c"
  21 #include "cpu/x86/mtrr/earlymtrr.c"
  22 #include "cpu/x86/bist.h"
  23 #include "northbridge/amd/amdk8/setup_resource_map.c"
  24 #include <spd.h>
  25 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  26
  27 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
  28
  29 static void memreset_setup(void)
  30 {
  31         if (is_cpu_pre_c0()) {
  32                 /* Set the memreset low. */
  33                 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
  34                 /* Ensure the BIOS has control of the memory lines. */
  35                 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  36         } else {
  37                 /* Ensure the CPU has control of the memory lines. */
  38                 outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
  39         }
  40 }
  41
  42 static void memreset(int controllers, const struct mem_controller *ctrl)
  43 {
  44         if (is_cpu_pre_c0()) {
  45                 udelay(800);
  46                 /* Set memreset high. */
  47                 outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
  48                 udelay(90);
  49         }
  50 }
  51
  52 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  53
  54 static inline int spd_read_byte(unsigned device, unsigned address)
  55 {
  56         return smbus_read_byte(device, address);
  57 }
  58
  59 #include "northbridge/amd/amdk8/raminit.c"
  60 #include "resourcemap.c"
  61 #include "northbridge/amd/amdk8/coherent_ht.c"
  62 #include "lib/generic_sdram.c"
  63 #include "cpu/amd/dualcore/dualcore.c"
  64 #include "cpu/amd/car/post_cache_as_ram.c"
  65 #include "cpu/amd/model_fxx/init_cpus.c"
  66 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  67 #include "northbridge/amd/amdk8/early_ht.c"
  68
  69 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  70 {
  71         static const struct mem_controller cpu[] = {
  72                 {
  73                         .node_id = 0,
  74                         .f0 = PCI_DEV(0, 0x18, 0),
  75                         .f1 = PCI_DEV(0, 0x18, 1),
  76                         .f2 = PCI_DEV(0, 0x18, 2),
  77                         .f3 = PCI_DEV(0, 0x18, 3),
  78                         .channel0 = { DIMM0, DIMM2, 0, 0 },
  79                         .channel1 = { DIMM1, DIMM3, 0, 0 },
  80                 },
  81 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  82                 {
  83                         .node_id = 1,
  84                         .f0 = PCI_DEV(0, 0x19, 0),
  85                         .f1 = PCI_DEV(0, 0x19, 1),
  86                         .f2 = PCI_DEV(0, 0x19, 2),
  87                         .f3 = PCI_DEV(0, 0x19, 3),
  88                         .channel0 = { DIMM4, DIMM6, 0, 0 },
  89                         .channel1 = { DIMM5, DIMM7, 0, 0 },
  90                 },
  91 #endif
  92         };
  93
  94         int needs_reset;
  95
  96         if (!cpu_init_detectedx && boot_cpu()) {
  97                 /* Nothing special needs to be done to find bus 0 */
  98                 /* Allow the HT devices to be found */
  99                 enumerate_ht_chain();
 100                 amd8111_enable_rom();
 101         }
 102
 103         if (bist == 0)
 104                 init_cpus(cpu_init_detectedx);
 105
 106         pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 107         uart_init();
 108         console_init();
 109
 110         /* Halt if there was a built in self test failure */
 111         report_bist_failure(bist);
 112
 113         setup_ibm_e325_resource_map();
 114
 115         needs_reset = setup_coherent_ht_domain();
 116
 117 #if CONFIG_LOGICAL_CPUS==1
 118         // It is said that we should start core1 after all core0 launched
 119         start_other_cores();
 120 #endif
 121         // automatically set that for you, but you might meet tight space
 122         needs_reset |= ht_setup_chains_x();
 123
 124         if (needs_reset) {
 125                 print_info("ht reset -\n");
 126                 soft_reset();
 127         }
 128
 129         enable_smbus();
 130
 131         memreset_setup();
 132         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 133
 134         post_cache_as_ram();
 135 }