1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
7 static void *smp_write_config_table(void *v)
9 static const char sig[4] = "PCMP";
10 static const char oem[8] = "COREBOOT";
11 static const char productid[12] = "E325 ";
12 struct mp_config_table *mc;
14 unsigned char bus_num;
15 unsigned char bus_isa;
16 unsigned char bus_8111_0;
17 unsigned char bus_8111_1;
18 unsigned char bus_8131_1;
19 unsigned char bus_8131_2;
21 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
22 memset(mc, 0, sizeof(*mc));
24 memcpy(mc->mpc_signature, sig, sizeof(sig));
25 mc->mpc_length = sizeof(*mc); /* initially just the header */
27 mc->mpc_checksum = 0; /* not yet computed */
28 memcpy(mc->mpc_oem, oem, sizeof(oem));
29 memcpy(mc->mpc_productid, productid, sizeof(productid));
32 mc->mpc_entry_count = 0; /* No entries yet... */
33 mc->mpc_lapic = LAPIC_ADDR;
38 smp_write_processors(mc);
44 dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
46 bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS);
47 bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
48 bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
51 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
58 dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
60 bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
63 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
68 dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
70 bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
72 printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
77 /* define bus and isa numbers */
78 for (bus_num = 0; bus_num < bus_isa; bus_num++) {
79 smp_write_bus(mc, bus_num, "PCI ");
81 smp_write_bus(mc, bus_isa, "ISA ");
83 /* Legacy IOAPIC #2 */
84 smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
89 dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
91 res = find_resource(dev, PCI_BASE_ADDRESS_0);
93 smp_write_ioapic(mc, 0x03, 0x11, res->base);
97 dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
99 res = find_resource(dev, PCI_BASE_ADDRESS_0);
101 smp_write_ioapic(mc, 0x04, 0x11, res->base);
106 /* ISA backward compatibility interrupts */
107 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, 0x02, 0x00);
108 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x01, 0x02, 0x01);
109 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, 0x02, 0x02);
110 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x03, 0x02, 0x03);
111 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x04, 0x02, 0x04);
112 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x05, 0x02, 0x05);
113 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x06, 0x02, 0x06);
114 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x07, 0x02, 0x07);
115 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x08, 0x02, 0x08);
116 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x09, 0x02, 0x09);
117 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x0a, 0x02, 0x0a);
118 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x0b, 0x02, 0x0b);
119 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x0c, 0x02, 0x0c);
120 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x0d, 0x02, 0x0d);
121 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x0e, 0x02, 0x0e);
122 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x0f, 0x02, 0x0f);
124 /* PCI Ints: Type Polarity Trigger Bus ID PCIDEVNUM|IRQ APIC ID PIN# */
125 /* Integrated SMBus 2.0 */
126 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|3, 0x2, 0x13);
127 /* Integrated AMD AC97 Audio */
128 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_0, (0x04<<2)|1, 0x2, 0x11);
130 /* Integrated AMD USB */
131 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x00<<2)|3, 0x2, 0x13);
133 /* On board ATI Rage XL */
134 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8111_1, (0x05<<2)|0, 0x2, 0x10);
136 /* On board Broadcom nics */
137 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, 0x3, 0x00);
138 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, 0x3, 0x01);
140 /* On board LSI SCSI */
141 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x02<<2)|0, 0x3, 0x02);
143 /* PCI Slot 1 PCIX */
144 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|0, 0x2, 0x10);
145 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|1, 0x2, 0x11);
146 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|2, 0x2, 0x12);
147 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x03<<2)|3, 0x2, 0x13);
149 /* PCI Slot 2 PCIX */
150 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|0, 0x2, 0x11);
151 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|1, 0x2, 0x12);
152 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|2, 0x2, 0x13);
153 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x04<<2)|3, 0x2, 0x10);
155 /* Standard local interrupt assignments:
156 * Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
157 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, MP_APIC_ALL, 0x00);
158 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, MP_APIC_ALL, 0x01);
160 /* There is no extension information... */
162 /* Compute the checksums */
163 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
164 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
165 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
166 mc, smp_next_mpe_entry(mc));
167 return smp_next_mpe_entry(mc);
170 unsigned long write_smp_table(unsigned long addr)
173 v = smp_write_floating_table(addr);
174 return (unsigned long)smp_write_config_table(v);