src/mainboard/ibase/mb899/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2010 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  18  */
  19
  20 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
  21
  22 #include <stdint.h>
  23 #include <string.h>
  24 #include <arch/io.h>
  25 #include <arch/romcc_io.h>
  26 #include <device/pci_def.h>
  27 #include <device/pnp_def.h>
  28 #include <cpu/x86/lapic.h>
  29 #include <lib.h>
  30 #include "superio/winbond/w83627ehg/w83627ehg.h"
  31 #include <pc80/mc146818rtc.h>
  32 #include <console/console.h>
  33 #include <usbdebug.h>
  34 #include <cpu/x86/bist.h>
  35 #include "superio/winbond/w83627ehg/early_serial.c"
  36 #include "northbridge/intel/i945/i945.h"
  37 #include "northbridge/intel/i945/raminit.h"
  38 #include "southbridge/intel/i82801gx/i82801gx.h"
  39
  40 #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
  41 #define DUMMY_DEV PNP_DEV(0x4e, 0)
  42
  43 void setup_ich7_gpios(void)
  44 {
  45         printk(BIOS_DEBUG, " GPIOS...");
  46         /* General Registers */
  47         outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00);      /* GPIO_USE_SEL */
  48         outl(0xe0e8efc3, DEFAULT_GPIOBASE + 0x04);      /* GP_IO_SEL */
  49         outl(0xebffeeff, DEFAULT_GPIOBASE + 0x0c);      /* GP_LVL */
  50         /* Output Control Registers */
  51         outl(0x00000000, DEFAULT_GPIOBASE + 0x18);      /* GPO_BLINK */
  52         /* Input Control Registers */
  53         outl(0x00002180, DEFAULT_GPIOBASE + 0x2c);      /* GPI_INV */
  54         outl(0x000100ff, DEFAULT_GPIOBASE + 0x30);      /* GPIO_USE_SEL2 */
  55         outl(0x00000030, DEFAULT_GPIOBASE + 0x34);      /* GP_IO_SEL2 */
  56         outl(0x00010035, DEFAULT_GPIOBASE + 0x38);      /* GP_LVL */
  57 }
  58
  59 static void ich7_enable_lpc(void)
  60 {
  61         // Enable Serial IRQ
  62         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
  63         // Set COM1/COM2 decode range
  64         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
  65         // Enable COM1/COM2/KBD/SuperIO1+2
  66         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b);
  67         // Enable HWM at 0x290
  68         pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0291);
  69         // io 0x300 decode
  70         pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
  71 }
  72
  73 /* This box has one superio
  74  * Also set up the GPIOs from the beginning. This is the "no schematic
  75  * but safe anyways" method.
  76  */
  77 static void early_superio_config_w83627ehg(void)
  78 {
  79         device_t dev;
  80
  81         dev = DUMMY_DEV;
  82         pnp_enter_ext_func_mode(dev);
  83
  84         pnp_write_config(dev, 0x24, 0xc4); // PNPCSV
  85
  86         pnp_write_config(dev, 0x29, 0x01); // GPIO settings
  87         pnp_write_config(dev, 0x2a, 0x40); // GPIO settings should be fc but gets set to 02
  88         pnp_write_config(dev, 0x2b, 0xc0); // GPIO settings?
  89         pnp_write_config(dev, 0x2c, 0x03); // GPIO settings?
  90         pnp_write_config(dev, 0x2d, 0x20); // GPIO settings?
  91
  92         dev=PNP_DEV(0x4e, W83627EHG_SP1);
  93         pnp_set_logical_device(dev);
  94         pnp_set_enable(dev, 0);
  95         pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
  96         pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
  97         pnp_set_enable(dev, 1);
  98
  99         dev=PNP_DEV(0x4e, W83627EHG_SP2);
 100         pnp_set_logical_device(dev);
 101         pnp_set_enable(dev, 0);
 102         pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8);
 103         pnp_set_irq(dev, PNP_IDX_IRQ0, 3);
 104         // pnp_write_config(dev, 0xf1, 4); // IRMODE0
 105         pnp_set_enable(dev, 1);
 106
 107         dev=PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard
 108         pnp_set_logical_device(dev);
 109         pnp_set_enable(dev, 0);
 110         pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
 111         pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
 112         //pnp_write_config(dev, 0xf0, 0x82);
 113         pnp_set_enable(dev, 1);
 114
 115         dev=PNP_DEV(0x4e, W83627EHG_GPIO2);
 116         pnp_set_logical_device(dev);
 117         pnp_set_enable(dev, 1); // Just enable it
 118
 119         dev=PNP_DEV(0x4e, W83627EHG_GPIO3);
 120         pnp_set_logical_device(dev);
 121         pnp_set_enable(dev, 0);
 122         pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output
 123         pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0
 124         pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient
 125
 126         dev=PNP_DEV(0x4e, W83627EHG_FDC);
 127         pnp_set_logical_device(dev);
 128         pnp_set_enable(dev, 0);
 129
 130         dev=PNP_DEV(0x4e, W83627EHG_PP);
 131         pnp_set_logical_device(dev);
 132         pnp_set_enable(dev, 0);
 133
 134         /* Enable HWM */
 135         dev=PNP_DEV(0x4e, W83627EHG_HWM);
 136         pnp_set_logical_device(dev);
 137         pnp_set_enable(dev, 0);
 138         pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
 139         pnp_set_enable(dev, 1);
 140
 141         pnp_exit_ext_func_mode(dev);
 142 }
 143
 144 static void rcba_config(void)
 145 {
 146         /* Set up virtual channel 0 */
 147         //RCBA32(0x0014) = 0x80000001;
 148         //RCBA32(0x001c) = 0x03128010;
 149
 150         /* Device 1f interrupt pin register */
 151         RCBA32(0x3100) = 0x00042210;
 152         /* Device 1d interrupt pin register */
 153         RCBA32(0x310c) = 0x00214321;
 154
 155         /* dev irq route register */
 156         RCBA16(0x3140) = 0x0132;
 157         RCBA16(0x3142) = 0x0146;
 158         RCBA16(0x3144) = 0x0237;
 159         RCBA16(0x3146) = 0x3201;
 160         RCBA16(0x3148) = 0x0146;
 161
 162         /* Enable IOAPIC */
 163         RCBA8(0x31ff) = 0x03;
 164
 165         /* Enable upper 128bytes of CMOS */
 166         RCBA32(0x3400) = (1 << 2);
 167
 168         /* Enable PCIe Root Port Clock Gate */
 169         // RCBA32(0x341c) = 0x00000001;
 170 }
 171
 172 static void early_ich7_init(void)
 173 {
 174         uint8_t reg8;
 175         uint32_t reg32;
 176
 177         // program secondary mlt XXX byte?
 178         pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
 179
 180         // reset rtc power status
 181         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
 182         reg8 &= ~(1 << 2);
 183         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
 184
 185         // usb transient disconnect
 186         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
 187         reg8 |= (3 << 0);
 188         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
 189
 190         reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
 191         reg32 |= (1 << 29) | (1 << 17);
 192         pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
 193
 194         reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
 195         reg32 |= (1 << 31) | (1 << 27);
 196         pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
 197
 198         RCBA32(0x0088) = 0x0011d000;
 199         RCBA16(0x01fc) = 0x060f;
 200         RCBA32(0x01f4) = 0x86000040;
 201         RCBA32(0x0214) = 0x10030549;
 202         RCBA32(0x0218) = 0x00020504;
 203         RCBA8(0x0220) = 0xc5;
 204         reg32 = RCBA32(0x3410);
 205         reg32 |= (1 << 6);
 206         RCBA32(0x3410) = reg32;
 207         reg32 = RCBA32(0x3430);
 208         reg32 &= ~(3 << 0);
 209         reg32 |= (1 << 0);
 210         RCBA32(0x3430) = reg32;
 211         RCBA32(0x3418) |= (1 << 0);
 212         RCBA16(0x0200) = 0x2008;
 213         RCBA8(0x2027) = 0x0d;
 214         RCBA16(0x3e08) |= (1 << 7);
 215         RCBA16(0x3e48) |= (1 << 7);
 216         RCBA32(0x3e0e) |= (1 << 7);
 217         RCBA32(0x3e4e) |= (1 << 7);
 218
 219         // next step only on ich7m b0 and later:
 220         reg32 = RCBA32(0x2034);
 221         reg32 &= ~(0x0f << 16);
 222         reg32 |= (5 << 16);
 223         RCBA32(0x2034) = reg32;
 224 }
 225
 226 #include <cbmem.h>
 227
 228 void main(unsigned long bist)
 229 {
 230         u32 reg32;
 231         int boot_mode = 0;
 232
 233         if (bist == 0)
 234                 enable_lapic();
 235
 236         ich7_enable_lpc();
 237         early_superio_config_w83627ehg();
 238
 239         /* Set up the console */
 240         console_init();
 241
 242         /* Halt if there was a built in self test failure */
 243         report_bist_failure(bist);
 244
 245         if (MCHBAR16(SSKPD) == 0xCAFE) {
 246                 printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
 247                 outb(0x6, 0xcf9);
 248                 while (1) asm("hlt");
 249         }
 250
 251         /* Perform some early chipset initialization required
 252          * before RAM initialization can work
 253          */
 254         i945_early_initialization();
 255
 256         /* Read PM1_CNT */
 257         reg32 = inl(DEFAULT_PMBASE + 0x04);
 258         printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
 259         if (((reg32 >> 10) & 7) == 5) {
 260 #if CONFIG_HAVE_ACPI_RESUME
 261                 printk(BIOS_DEBUG, "Resume from S3 detected.\n");
 262                 boot_mode = 2;
 263                 /* Clear SLP_TYPE. This will break stage2 but
 264                  * we care for that when we get there.
 265                  */
 266                 outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
 267 #else
 268                 printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
 269 #endif
 270         }
 271
 272         /* Enable SPD ROMs and DDR-II DRAM */
 273         enable_smbus();
 274
 275 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
 276         dump_spd_registers();
 277 #endif
 278
 279         sdram_initialize(boot_mode, NULL);
 280
 281         /* Perform some initialization that must run before stage2 */
 282         early_ich7_init();
 283
 284         /* This should probably go away. Until now it is required
 285          * and mainboard specific
 286          */
 287         rcba_config();
 288
 289         /* Chipset Errata! */
 290         fixup_i945_errata();
 291
 292         /* Initialize the internal PCIe links before we go into stage2 */
 293         i945_late_initialization();
 294
 295 #if !CONFIG_HAVE_ACPI_RESUME
 296 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
 297 #if CONFIG_DEBUG_RAM_SETUP
 298         sdram_dump_mchbar_registers();
 299 #endif
 300
 301         {
 302                 /* This will not work if TSEG is in place! */
 303                 u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
 304
 305                 printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
 306                 ram_check(0x00000000, 0x000a0000);
 307                 //ram_check(0x00100000, tom);
 308         }
 309 #endif
 310 #endif
 311
 312         quick_ram_check();
 313
 314         MCHBAR16(SSKPD) = 0xCAFE;
 315
 316 #if CONFIG_HAVE_ACPI_RESUME
 317         /* Start address of high memory tables */
 318         unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
 319
 320         /* If there is no high memory area, we didn't boot before, so
 321          * this is not a resume. In that case we just create the cbmem toc.
 322          */
 323         if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) {
 324                 void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
 325
 326                 /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
 327                  * through stage 2. We could keep stuff like stack and heap in high tables
 328                  * memory completely, but that's a wonderful clean up task for another
 329                  * day.
 330                  */
 331                 if (resume_backup_memory)
 332                         memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
 333
 334                 /* Magic for S3 resume */
 335                 pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
 336         }
 337 #endif
 338 }