src/mainboard/ibase/mb899/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007-2010 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  18  */
  19
  20 // __PRE_RAM__ means: use "unsigned" for device, not a struct.
  21
  22 #include <stdint.h>
  23 #include <string.h>
  24 #include <arch/io.h>
  25 #include <arch/romcc_io.h>
  26 #include <device/pci_def.h>
  27 #include <device/pnp_def.h>
  28 #include <cpu/x86/lapic.h>
  29 #include <lib.h>
  30 #include "superio/winbond/w83627ehg/w83627ehg.h"
  31 #include <pc80/mc146818rtc.h>
  32 #include <console/console.h>
  33 #include <cpu/x86/bist.h>
  34 #include "superio/winbond/w83627ehg/early_serial.c"
  35 #include "northbridge/intel/i945/i945.h"
  36 #include "northbridge/intel/i945/raminit.h"
  37 #include "southbridge/intel/i82801gx/i82801gx.h"
  38
  39 #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
  40 #define DUMMY_DEV PNP_DEV(0x4e, 0)
  41
  42 void setup_ich7_gpios(void)
  43 {
  44         printk(BIOS_DEBUG, " GPIOS...");
  45         /* General Registers */
  46         outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00);      /* GPIO_USE_SEL */
  47         outl(0xe0e8efc3, DEFAULT_GPIOBASE + 0x04);      /* GP_IO_SEL */
  48         outl(0xebffeeff, DEFAULT_GPIOBASE + 0x0c);      /* GP_LVL */
  49         /* Output Control Registers */
  50         outl(0x00000000, DEFAULT_GPIOBASE + 0x18);      /* GPO_BLINK */
  51         /* Input Control Registers */
  52         outl(0x00002180, DEFAULT_GPIOBASE + 0x2c);      /* GPI_INV */
  53         outl(0x000100ff, DEFAULT_GPIOBASE + 0x30);      /* GPIO_USE_SEL2 */
  54         outl(0x00000030, DEFAULT_GPIOBASE + 0x34);      /* GP_IO_SEL2 */
  55         outl(0x00010035, DEFAULT_GPIOBASE + 0x38);      /* GP_LVL */
  56 }
  57
  58 static void ich7_enable_lpc(void)
  59 {
  60         // Enable Serial IRQ
  61         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
  62         // Set COM1/COM2 decode range
  63         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
  64         // Enable COM1/COM2/KBD/SuperIO1+2
  65         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b);
  66         // Enable HWM at 0x290
  67         pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0291);
  68         // io 0x300 decode
  69         pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
  70 }
  71
  72 /* This box has one superio
  73  * Also set up the GPIOs from the beginning. This is the "no schematic
  74  * but safe anyways" method.
  75  */
  76 static void early_superio_config_w83627ehg(void)
  77 {
  78         device_t dev;
  79
  80         dev = DUMMY_DEV;
  81         pnp_enter_ext_func_mode(dev);
  82
  83         pnp_write_config(dev, 0x24, 0xc4); // PNPCSV
  84
  85         pnp_write_config(dev, 0x29, 0x01); // GPIO settings
  86         pnp_write_config(dev, 0x2a, 0x40); // GPIO settings should be fc but gets set to 02
  87         pnp_write_config(dev, 0x2b, 0xc0); // GPIO settings?
  88         pnp_write_config(dev, 0x2c, 0x03); // GPIO settings?
  89         pnp_write_config(dev, 0x2d, 0x20); // GPIO settings?
  90
  91         dev=PNP_DEV(0x4e, W83627EHG_SP1);
  92         pnp_set_logical_device(dev);
  93         pnp_set_enable(dev, 0);
  94         pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
  95         pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
  96         pnp_set_enable(dev, 1);
  97
  98         dev=PNP_DEV(0x4e, W83627EHG_SP2);
  99         pnp_set_logical_device(dev);
 100         pnp_set_enable(dev, 0);
 101         pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8);
 102         pnp_set_irq(dev, PNP_IDX_IRQ0, 3);
 103         // pnp_write_config(dev, 0xf1, 4); // IRMODE0
 104         pnp_set_enable(dev, 1);
 105
 106         dev=PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard
 107         pnp_set_logical_device(dev);
 108         pnp_set_enable(dev, 0);
 109         pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
 110         pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
 111         //pnp_write_config(dev, 0xf0, 0x82);
 112         pnp_set_enable(dev, 1);
 113
 114         dev=PNP_DEV(0x4e, W83627EHG_GPIO2);
 115         pnp_set_logical_device(dev);
 116         pnp_set_enable(dev, 1); // Just enable it
 117
 118         dev=PNP_DEV(0x4e, W83627EHG_GPIO3);
 119         pnp_set_logical_device(dev);
 120         pnp_set_enable(dev, 0);
 121         pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output
 122         pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0
 123         pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient
 124
 125         dev=PNP_DEV(0x4e, W83627EHG_FDC);
 126         pnp_set_logical_device(dev);
 127         pnp_set_enable(dev, 0);
 128
 129         dev=PNP_DEV(0x4e, W83627EHG_PP);
 130         pnp_set_logical_device(dev);
 131         pnp_set_enable(dev, 0);
 132
 133         /* Enable HWM */
 134         dev=PNP_DEV(0x4e, W83627EHG_HWM);
 135         pnp_set_logical_device(dev);
 136         pnp_set_enable(dev, 0);
 137         pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
 138         pnp_set_enable(dev, 1);
 139
 140         pnp_exit_ext_func_mode(dev);
 141 }
 142
 143 static void rcba_config(void)
 144 {
 145         /* Set up virtual channel 0 */
 146         //RCBA32(0x0014) = 0x80000001;
 147         //RCBA32(0x001c) = 0x03128010;
 148
 149         /* Device 1f interrupt pin register */
 150         RCBA32(0x3100) = 0x00042210;
 151         /* Device 1d interrupt pin register */
 152         RCBA32(0x310c) = 0x00214321;
 153
 154         /* dev irq route register */
 155         RCBA16(0x3140) = 0x0132;
 156         RCBA16(0x3142) = 0x0146;
 157         RCBA16(0x3144) = 0x0237;
 158         RCBA16(0x3146) = 0x3201;
 159         RCBA16(0x3148) = 0x0146;
 160
 161         /* Enable IOAPIC */
 162         RCBA8(0x31ff) = 0x03;
 163
 164         /* Enable upper 128bytes of CMOS */
 165         RCBA32(0x3400) = (1 << 2);
 166
 167         /* Enable PCIe Root Port Clock Gate */
 168         // RCBA32(0x341c) = 0x00000001;
 169 }
 170
 171 static void early_ich7_init(void)
 172 {
 173         uint8_t reg8;
 174         uint32_t reg32;
 175
 176         // program secondary mlt XXX byte?
 177         pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
 178
 179         // reset rtc power status
 180         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
 181         reg8 &= ~(1 << 2);
 182         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
 183
 184         // usb transient disconnect
 185         reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
 186         reg8 |= (3 << 0);
 187         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
 188
 189         reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
 190         reg32 |= (1 << 29) | (1 << 17);
 191         pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
 192
 193         reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
 194         reg32 |= (1 << 31) | (1 << 27);
 195         pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
 196
 197         RCBA32(0x0088) = 0x0011d000;
 198         RCBA16(0x01fc) = 0x060f;
 199         RCBA32(0x01f4) = 0x86000040;
 200         RCBA32(0x0214) = 0x10030549;
 201         RCBA32(0x0218) = 0x00020504;
 202         RCBA8(0x0220) = 0xc5;
 203         reg32 = RCBA32(0x3410);
 204         reg32 |= (1 << 6);
 205         RCBA32(0x3410) = reg32;
 206         reg32 = RCBA32(0x3430);
 207         reg32 &= ~(3 << 0);
 208         reg32 |= (1 << 0);
 209         RCBA32(0x3430) = reg32;
 210         RCBA32(0x3418) |= (1 << 0);
 211         RCBA16(0x0200) = 0x2008;
 212         RCBA8(0x2027) = 0x0d;
 213         RCBA16(0x3e08) |= (1 << 7);
 214         RCBA16(0x3e48) |= (1 << 7);
 215         RCBA32(0x3e0e) |= (1 << 7);
 216         RCBA32(0x3e4e) |= (1 << 7);
 217
 218         // next step only on ich7m b0 and later:
 219         reg32 = RCBA32(0x2034);
 220         reg32 &= ~(0x0f << 16);
 221         reg32 |= (5 << 16);
 222         RCBA32(0x2034) = reg32;
 223 }
 224
 225 #include <cbmem.h>
 226
 227 void main(unsigned long bist)
 228 {
 229         u32 reg32;
 230         int boot_mode = 0;
 231
 232         if (bist == 0)
 233                 enable_lapic();
 234
 235         ich7_enable_lpc();
 236         early_superio_config_w83627ehg();
 237
 238         /* Set up the console */
 239         console_init();
 240
 241         /* Halt if there was a built in self test failure */
 242         report_bist_failure(bist);
 243
 244         if (MCHBAR16(SSKPD) == 0xCAFE) {
 245                 printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
 246                 outb(0x6, 0xcf9);
 247                 while (1) asm("hlt");
 248         }
 249
 250         /* Perform some early chipset initialization required
 251          * before RAM initialization can work
 252          */
 253         i945_early_initialization();
 254
 255         /* Read PM1_CNT */
 256         reg32 = inl(DEFAULT_PMBASE + 0x04);
 257         printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
 258         if (((reg32 >> 10) & 7) == 5) {
 259 #if CONFIG_HAVE_ACPI_RESUME
 260                 printk(BIOS_DEBUG, "Resume from S3 detected.\n");
 261                 boot_mode = 2;
 262                 /* Clear SLP_TYPE. This will break stage2 but
 263                  * we care for that when we get there.
 264                  */
 265                 outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
 266 #else
 267                 printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
 268 #endif
 269         }
 270
 271         /* Enable SPD ROMs and DDR-II DRAM */
 272         enable_smbus();
 273
 274 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
 275         dump_spd_registers();
 276 #endif
 277
 278         sdram_initialize(boot_mode, NULL);
 279
 280         /* Perform some initialization that must run before stage2 */
 281         early_ich7_init();
 282
 283         /* This should probably go away. Until now it is required
 284          * and mainboard specific
 285          */
 286         rcba_config();
 287
 288         /* Chipset Errata! */
 289         fixup_i945_errata();
 290
 291         /* Initialize the internal PCIe links before we go into stage2 */
 292         i945_late_initialization();
 293
 294 #if !CONFIG_HAVE_ACPI_RESUME
 295 #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
 296 #if CONFIG_DEBUG_RAM_SETUP
 297         sdram_dump_mchbar_registers();
 298 #endif
 299
 300         {
 301                 /* This will not work if TSEG is in place! */
 302                 u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
 303
 304                 printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
 305                 ram_check(0x00000000, 0x000a0000);
 306                 //ram_check(0x00100000, tom);
 307         }
 308 #endif
 309 #endif
 310
 311         quick_ram_check();
 312
 313         MCHBAR16(SSKPD) = 0xCAFE;
 314
 315 #if CONFIG_HAVE_ACPI_RESUME
 316         /* Start address of high memory tables */
 317         unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
 318
 319         /* If there is no high memory area, we didn't boot before, so
 320          * this is not a resume. In that case we just create the cbmem toc.
 321          */
 322         if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) {
 323                 void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
 324
 325                 /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
 326                  * through stage 2. We could keep stuff like stack and heap in high tables
 327                  * memory completely, but that's a wonderful clean up task for another
 328                  * day.
 329                  */
 330                 if (resume_backup_memory)
 331                         memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
 332
 333                 /* Magic for S3 resume */
 334                 pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_ACPI_S3_MAGIC);
 335         }
 336 #endif
 337 }