Move "select CACHE_AS_RAM" lines from boards into CPU socket.
[coreboot.git] / src / mainboard / ibase / mb899 / Kconfig
1 if BOARD_IBASE_MB899
2
3 config BOARD_SPECIFIC_OPTIONS # dummy
4         def_bool y
5         select ARCH_X86
6         select CPU_INTEL_CORE
7         select CPU_INTEL_SOCKET_MFCPGA478
8         select NORTHBRIDGE_INTEL_I945GM
9         select SOUTHBRIDGE_INTEL_I82801GX
10         select SUPERIO_WINBOND_W83627EHG
11         select BOARD_HAS_FADT
12         select HAVE_ACPI_TABLES
13         select HAVE_PIRQ_TABLE
14         select HAVE_MP_TABLE
15         select HAVE_OPTION_TABLE
16         select HAVE_ACPI_RESUME
17         select MMCONF_SUPPORT
18         select HAVE_SMI_HANDLER
19         select BOARD_ROMSIZE_KB_512
20         select GFXUMA
21         select TINY_BOOTBLOCK
22         select CHANNEL_XOR_RANDOMIZATION
23
24 config MAINBOARD_DIR
25         string
26         default ibase/mb899
27
28 config DCACHE_RAM_BASE
29         hex
30         default 0xffdf8000
31
32 config DCACHE_RAM_SIZE
33         hex
34         default 0x8000
35
36 config MAINBOARD_PART_NUMBER
37         string
38         default "MB899"
39
40 config MMCONF_BASE_ADDRESS
41         hex
42         default 0xf0000000
43
44 config IRQ_SLOT_COUNT
45         int
46         default 18
47
48 config MAX_CPUS
49         int
50         default 4
51
52 config MAX_PHYSICAL_CPUS
53         int
54         default 2
55
56 config FALLBACK_VGA_BIOS_FILE
57         string
58         default "amipci_01.20"
59
60 endif # BOARD_IBASE_MB899