2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 Tyan
5 * Copyright (C) 2006 AMD
6 * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD.
8 * Copyright (C) 2007 University of Mannheim
9 * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim
10 * Copyright (C) 2009 University of Heidelberg
11 * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 #define FAM10_SCAN_PCI_BUS 0
29 #define FAM10_ALLOCATE_IO_RANGE 1
33 #include <device/pci_def.h>
34 #include <device/pci_ids.h>
36 #include <device/pnp_def.h>
37 #include <arch/romcc_io.h>
38 #include <cpu/x86/lapic.h>
39 #include "option_table.h"
40 #include <console/console.h>
41 #include <cpu/amd/model_10xxx_rev.h>
42 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
43 #include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
44 #include "northbridge/amd/amdfam10/raminit.h"
45 #include "northbridge/amd/amdfam10/amdfam10.h"
48 #include "cpu/amd/model_10xxx/apic_timer.c"
49 #include "lib/delay.c"
50 #include "cpu/x86/lapic/boot_cpu.c"
51 #include "northbridge/amd/amdfam10/reset_test.c"
53 #include "superio/serverengines/pilot/pilot_early_serial.c"
54 #include "superio/serverengines/pilot/pilot_early_init.c"
55 #include "superio/nsc/pc87417/pc87417_early_serial.c"
57 #include "cpu/x86/bist.h"
59 #include "northbridge/amd/amdfam10/debug.c"
61 #include "cpu/x86/mtrr/earlymtrr.c"
63 //#include "northbridge/amd/amdfam10/setup_resource_map.c"
65 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
66 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
68 #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
70 static inline void activate_spd_rom(const struct mem_controller *ctrl)
78 outb((val & ~3) | ctrl->spd_switch_addr, 0xcd7);
81 static inline int spd_read_byte(unsigned device, unsigned address)
83 return smbus_read_byte(device, address);
86 #include "northbridge/amd/amdfam10/amdfam10.h"
88 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
89 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
91 #include "cpu/amd/quadcore/quadcore.c"
93 #include "cpu/amd/car/post_cache_as_ram.c"
95 #include "cpu/amd/microcode/microcode.c"
96 #include "cpu/amd/model_10xxx/update_microcode.c"
97 #include "cpu/amd/model_10xxx/init_cpus.c"
99 #include "northbridge/amd/amdfam10/early_ht.c"
101 #include "spd_addr.h"
103 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
105 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
112 if (!cpu_init_detectedx && boot_cpu()) {
113 /* Nothing special needs to be done to find bus 0 */
114 /* Allow the HT devices to be found */
115 /* mov bsp to bus 0xff when > 8 nodes */
116 set_bsp_node_CHtExtNodeCfgEn();
117 enumerate_ht_chain();
119 /* Setup the rom access for 4M */
120 bcm5785_enable_rom();
121 bcm5785_enable_lpc();
123 pc87417_enable_dev(RTC_DEV);
129 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
132 pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
136 /* Halt if there was a built in self test failure */
137 report_bist_failure(bist);
140 pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV
143 printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
144 printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
145 printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
146 printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
148 /* Setup sysinfo defaults */
149 set_sysinfo_in_ram(0);
151 update_microcode(val);
157 amd_ht_init(sysinfo);
160 /* Setup nodes PCI space and start core 0 AP init. */
161 finalize_node_setup(sysinfo);
165 /* wait for all the APs core0 started by finalize_node_setup. */
166 /* FIXME: A bunch of cores are going to start output to serial at once.
167 * It would be nice to fixup prink spinlocks for ROM XIP mode.
168 * I think it could be done by putting the spinlock flag in the cache
169 * of the BSP located right after sysinfo.
172 wait_all_core0_started();
174 #if CONFIG_LOGICAL_CPUS==1
175 /* Core0 on each node is configured. Now setup any additional cores. */
176 printk(BIOS_DEBUG, "start_other_cores()\n");
179 wait_all_other_cores_started(bsp_apicid);
182 #if CONFIG_SET_FIDVID
183 msr = rdmsr(0xc0010071);
184 printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
186 /* FIXME: The sb fid change may survive the warm reset and only
187 * need to be done once.*/
189 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
193 if (!warm_reset_detect(0)) { // BSP is node 0
194 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
196 init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
201 /* show final fid and vid */
202 msr=rdmsr(0xc0010071);
203 printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
208 /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
209 if (!warm_reset_detect(0)) {
210 print_info("...WARM RESET...\n\n\n");
212 die("After soft_reset_x - shouldn't see this message!!!\n");
215 /* It's the time to set ctrl in sysinfo now; */
216 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
219 //do we need apci timer, tsc...., only debug need it for better output
220 /* all ap stopped? */
221 // init_timer(); // Need to use TMICT to synconize FID/VID
223 printk(BIOS_DEBUG, "raminit_amdmct()\n");
224 raminit_amdmct(sysinfo);
227 bcm5785_early_setup();