src/mainboard/hp/dl165_g6_fam10/mptable.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2001 Eric W.Biederman<ebiderman@lnxi.com>
   5  *
   6  * Copyright (C) 2006 AMD
   7  * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
   8  *
   9  * Copyright (C) 2007 University of Mannheim
  10  * Written by Philipp Degler <pdegler@rumms.uni-mannheim.e> for Uni of Mannheim
  11  *
  12  * Copyright (C) 2009 University of Heidelberg
  13  * Written by Mondrian Nuessle <nuessle@uni-hd.de> for Uni of Heidelberg
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  28  */
  29
  30 #include <console/console.h>
  31 #include <arch/smp/mpspec.h>
  32 #include <arch/io.h>
  33 #include <device/pci.h>
  34 #include <string.h>
  35 #include <stdint.h>
  36 #if CONFIG_LOGICAL_CPUS==1
  37 #include <cpu/amd/multicore.h>
  38 #endif
  39
  40 #include <cpu/amd/amdfam10_sysconf.h>
  41
  42 #include "mb_sysconf.h"
  43
  44 static void *smp_write_config_table(void *v)
  45 {
  46         static const char sig[4] = "PCMP";
  47         static const char oem[8] = "COREBOOT";
  48         static const char productid[12] = "HP DL165 G6 ";
  49         struct mp_config_table *mc;
  50         int isa_bus;
  51
  52         struct mb_sysconf_t *m;
  53
  54         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  55         memset(mc, 0, sizeof(*mc));
  56
  57         memcpy(mc->mpc_signature, sig, sizeof(sig));
  58         mc->mpc_length = sizeof(*mc); /* initially just the header */
  59         mc->mpc_spec = 0x04;
  60         mc->mpc_checksum = 0; /* not yet computed */
  61         memcpy(mc->mpc_oem, oem, sizeof(oem));
  62         memcpy(mc->mpc_productid, productid, sizeof(productid));
  63         mc->mpc_oemptr = 0;
  64         mc->mpc_oemsize = 0;
  65         mc->mpc_entry_count = 0; /* No entries yet... */
  66         mc->mpc_lapic = LAPIC_ADDR;
  67         mc->mpe_length = 0;
  68         mc->mpe_checksum = 0;
  69         mc->reserved = 0;
  70
  71         smp_write_processors(mc);
  72
  73         get_bus_conf();
  74         m = sysconf.mb;
  75
  76         mptable_write_buses(mc, NULL, &isa_bus);
  77         printk(BIOS_DEBUG, "writing %d as ISA to mptable (%d for real)...\n", isa_bus, m->bus_isa);
  78
  79         /*I/O APICs:   APIC ID Version State           Address*/
  80         {
  81                 device_t dev = 0;
  82                 int i;
  83                 struct resource *res;
  84                 for(i=0; i<3; i++) {
  85                         dev = dev_find_device(0x1166, 0x0235, dev);
  86                         if (dev) {
  87                                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
  88                                 if (res) {
  89                                         printk(BIOS_DEBUG, "APIC %d base address: %x\n",m->apicid_bcm5785[i], (int)res->base);
  90                                         smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base);
  91                                 }
  92                         }
  93                 }
  94
  95         }
  96
  97         /* IRQ routing as factory BIOS */
  98         outb(0x00, 0xc00); outb(0x09, 0xc01);
  99         outb(0x01, 0xc00); outb(0x0a, 0xc01);
 100         outb(0x02, 0xc00); outb(0x0e, 0xc01);
 101         outb(0x03, 0xc00); outb(0x07, 0xc01);
 102         outb(0x07, 0xc00); outb(0x05, 0xc01);
 103
 104         // 8259 registers...
 105         outb(0xa0, 0x4d0);
 106         outb(0x0e, 0x4d1);
 107
 108         {
 109                 device_t dev;
 110                 dev = dev_find_device(0x1166, 0x0205, 0);
 111                 if(dev) {
 112                         uint32_t dword;
 113                         dword = pci_read_config32(dev, 0x64);
 114                         dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7
 115                         pci_write_config32(dev, 0x64, dword);
 116                 }
 117                 // set GEVENT pins to NO OP
 118                 /* outb(0x33, 0xcd6); outb(0x00, 0xcd7);
 119                 outb(0x34, 0xcd6); outb(0x00, 0xcd7);
 120                 outb(0x35, 0xcd6); outb(0x00, 0xcd7); */
 121         }
 122
 123         // hide XIOAPIC PCI configuration space
 124         {
 125                 device_t dev;
 126                 dev = dev_find_device(0x1166, 0x205, 0);
 127                 if (dev) {
 128                         uint32_t dword;
 129                         dword = pci_read_config32(dev, 0x64);
 130                         dword |= (1<<26);
 131                         pci_write_config32(dev, 0x64, dword);
 132                 }
 133         }
 134
 135         mptable_add_isa_interrupts(mc, isa_bus, m->apicid_bcm5785[0], 0);
 136
 137         /* I/O Ints:            Type    Polarity/Trigger                        Bus ID          IRQ     APIC ID         PIN#  */
 138         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0xe<<2)|0,    m->apicid_bcm5785[0], 0x5);
 139         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x3<<2)|0,    m->apicid_bcm5785[0], 0xa);
 140         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6<<2)|0,    m->apicid_bcm5785[2], 0x4);
 141         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7<<2)|0,    m->apicid_bcm5785[2], 0x3);
 142         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8<<2)|0,    m->apicid_bcm5785[2], 0x2);
 143         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9<<2)|0,    m->apicid_bcm5785[2], 0x1);
 144         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa<<2)|0,    m->apicid_bcm5785[2], 0x0);
 145         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2<<2)|0,  m->apicid_bcm5785[2], 0x8);
 146         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2<<2)|1,  m->apicid_bcm5785[2], 0x7);
 147         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0x0<<2)|0,   m->apicid_bcm5785[2], 0xa);
 148
 149         /* enable int */
 150         /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
 151         {
 152                 device_t dev;
 153                 dev = dev_find_device(0x1166, 0x0205, 0);
 154                 if(dev) {
 155                         uint32_t dword;
 156                         dword = pci_read_config32(dev, 0x6c);
 157                         dword |= (1<<4); // enable interrupts
 158                         printk(BIOS_DEBUG, "6ch: %x\n",dword);
 159                         pci_write_config32(dev, 0x6c, dword);
 160                 }
 161         }
 162
 163         /* Local Ints:          Type    Polarity/Trigger                                Bus ID          IRQ     APIC ID         PIN#  */
 164         smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus,        0x0,    MP_APIC_ALL,    0x0);
 165         smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus,           0x0,    MP_APIC_ALL,    0x1);
 166
 167         //extended table entries
 168         smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001);
 169         smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x7f80, 0x0, 0x5e80);
 170         smp_write_address_space(mc,0 , ADDRESS_TYPE_PREFETCH, 0x0, 0xde00, 0x0, 0x0100);
 171         smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0xdf00, 0x0, 0x1fe0);
 172         smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x1000, 0xfee0, 0xf000, 0x011f);
 173         smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x000a, 0x0, 0x0006);
 174         smp_write_bus_hierarchy(mc, 8, 0x01, 0);
 175         smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 0);
 176         smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 1);
 177
 178
 179         /* Compute the checksums */
 180         mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 181         mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 182         printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 183                 mc, smp_next_mpe_entry(mc));
 184         return smp_next_mpe_entry(mc);
 185 }
 186
 187 unsigned long write_smp_table(unsigned long addr)
 188 {
 189         void *v;
 190         v = smp_write_floating_table(addr);
 191         return (unsigned long)smp_write_config_table(v);
 192 }