src/mainboard/hp/dl165_g6_fam10/mptable.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2001 Eric W.Biederman<ebiderman@lnxi.com>
   5  *
   6  * Copyright (C) 2006 AMD
   7  * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
   8  *
   9  * Copyright (C) 2007 University of Mannheim
  10  * Written by Philipp Degler <pdegler@rumms.uni-mannheim.e> for Uni of Mannheim
  11  *
  12  * Copyright (C) 2009 University of Heidelberg
  13  * Written by Mondrian Nuessle <nuessle@uni-hd.de> for Uni of Heidelberg
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  28  */
  29
  30 #include <console/console.h>
  31 #include <arch/smp/mpspec.h>
  32 #include <arch/io.h>
  33 #include <device/pci.h>
  34 #include <string.h>
  35 #include <stdint.h>
  36 #if CONFIG_LOGICAL_CPUS==1
  37 #include <cpu/amd/multicore.h>
  38 #endif
  39 #include <cpu/amd/amdfam10_sysconf.h>
  40 #include "mb_sysconf.h"
  41
  42 static void *smp_write_config_table(void *v)
  43 {
  44         struct mp_config_table *mc;
  45         int isa_bus;
  46
  47         struct mb_sysconf_t *m;
  48
  49         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  50
  51         mptable_init(mc, LOCAL_APIC_ADDR);
  52
  53         smp_write_processors(mc);
  54
  55         get_bus_conf();
  56         m = sysconf.mb;
  57
  58         mptable_write_buses(mc, NULL, &isa_bus);
  59
  60         /*I/O APICs:   APIC ID Version State           Address*/
  61         {
  62                 device_t dev = 0;
  63                 int i;
  64                 struct resource *res;
  65                 for(i=0; i<3; i++) {
  66                         dev = dev_find_device(0x1166, 0x0235, dev);
  67                         if (dev) {
  68                                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
  69                                 if (res) {
  70                                         printk(BIOS_DEBUG, "APIC %d base address: %x\n",m->apicid_bcm5785[i], (int)res->base);
  71                                         smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base);
  72                                 }
  73                         }
  74                 }
  75
  76         }
  77
  78         /* IRQ routing as factory BIOS */
  79         outb(0x00, 0xc00); outb(0x09, 0xc01);
  80         outb(0x01, 0xc00); outb(0x0a, 0xc01);
  81         outb(0x02, 0xc00); outb(0x0e, 0xc01);
  82         outb(0x03, 0xc00); outb(0x07, 0xc01);
  83         outb(0x07, 0xc00); outb(0x05, 0xc01);
  84
  85         // 8259 registers...
  86         outb(0xa0, 0x4d0);
  87         outb(0x0e, 0x4d1);
  88
  89         {
  90                 device_t dev;
  91                 dev = dev_find_device(0x1166, 0x0205, 0);
  92                 if(dev) {
  93                         uint32_t dword;
  94                         dword = pci_read_config32(dev, 0x64);
  95                         dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7
  96                         pci_write_config32(dev, 0x64, dword);
  97                 }
  98                 // set GEVENT pins to NO OP
  99                 /* outb(0x33, 0xcd6); outb(0x00, 0xcd7);
 100                 outb(0x34, 0xcd6); outb(0x00, 0xcd7);
 101                 outb(0x35, 0xcd6); outb(0x00, 0xcd7); */
 102         }
 103
 104         // hide XIOAPIC PCI configuration space
 105         {
 106                 device_t dev;
 107                 dev = dev_find_device(0x1166, 0x205, 0);
 108                 if (dev) {
 109                         uint32_t dword;
 110                         dword = pci_read_config32(dev, 0x64);
 111                         dword |= (1<<26);
 112                         pci_write_config32(dev, 0x64, dword);
 113                 }
 114         }
 115
 116         mptable_add_isa_interrupts(mc, isa_bus, m->apicid_bcm5785[0], 0);
 117
 118         /* I/O Ints:            Type    Polarity/Trigger                        Bus ID          IRQ     APIC ID         PIN#  */
 119         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0xe<<2)|0,    m->apicid_bcm5785[0], 0x5);
 120         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x3<<2)|0,    m->apicid_bcm5785[0], 0xa);
 121         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6<<2)|0,    m->apicid_bcm5785[2], 0x4);
 122         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7<<2)|0,    m->apicid_bcm5785[2], 0x3);
 123         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8<<2)|0,    m->apicid_bcm5785[2], 0x2);
 124         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9<<2)|0,    m->apicid_bcm5785[2], 0x1);
 125         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa<<2)|0,    m->apicid_bcm5785[2], 0x0);
 126         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2<<2)|0,  m->apicid_bcm5785[2], 0x8);
 127         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1_1, (0x2<<2)|1,  m->apicid_bcm5785[2], 0x7);
 128         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5780[5], (0x0<<2)|0,   m->apicid_bcm5785[2], 0xa);
 129
 130         /* enable int */
 131         /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
 132         {
 133                 device_t dev;
 134                 dev = dev_find_device(0x1166, 0x0205, 0);
 135                 if(dev) {
 136                         uint32_t dword;
 137                         dword = pci_read_config32(dev, 0x6c);
 138                         dword |= (1<<4); // enable interrupts
 139                         printk(BIOS_DEBUG, "6ch: %x\n",dword);
 140                         pci_write_config32(dev, 0x6c, dword);
 141                 }
 142         }
 143
 144         /* Local Ints:          Type    Polarity/Trigger                                Bus ID          IRQ     APIC ID         PIN#  */
 145         mptable_lintsrc(mc, isa_bus);
 146
 147         //extended table entries
 148         smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001);
 149         smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x7f80, 0x0, 0x5e80);
 150         smp_write_address_space(mc,0 , ADDRESS_TYPE_PREFETCH, 0x0, 0xde00, 0x0, 0x0100);
 151         smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0xdf00, 0x0, 0x1fe0);
 152         smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x1000, 0xfee0, 0xf000, 0x011f);
 153         smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x000a, 0x0, 0x0006);
 154         smp_write_bus_hierarchy(mc, 8, 0x01, 0);
 155         smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 0);
 156         smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 1);
 157
 158
 159         /* Compute the checksums */
 160         return mptable_finalize(mc);
 161 }
 162
 163 unsigned long write_smp_table(unsigned long addr)
 164 {
 165         void *v;
 166         v = smp_write_floating_table(addr, 0);
 167         return (unsigned long)smp_write_config_table(v);
 168 }