src/mainboard/hp/dl145_g3/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 Tyan
   5  * Copyright (C) 2006 AMD
   6  * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD.
   7  *
   8  * Copyright (C) 2007 University of Mannheim
   9  * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim
  10  * Copyright (C) 2009 University of Heidelberg
  11  * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  26  */
  27
  28 #if CONFIG_LOGICAL_CPUS==1
  29 #define SET_NB_CFG_54 1
  30 #endif
  31
  32 #if CONFIG_K8_REV_F_SUPPORT == 1
  33 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  34 #endif
  35
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <device/pci_def.h>
  39 #include <device/pci_ids.h>
  40 #include <arch/io.h>
  41 #include <device/pnp_def.h>
  42 #include <arch/romcc_io.h>
  43 #include <cpu/x86/lapic.h>
  44 #include <pc80/mc146818rtc.h>
  45
  46 #include <console/console.h>
  47
  48 #include <cpu/amd/model_fxx_rev.h>
  49
  50 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
  51 #include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
  52 #include "northbridge/amd/amdk8/raminit.h"
  53 #include "cpu/amd/model_fxx/apic_timer.c"
  54 #include "lib/delay.c"
  55
  56 #include "cpu/x86/lapic/boot_cpu.c"
  57 #include "northbridge/amd/amdk8/reset_test.c"
  58
  59 #include "superio/serverengines/pilot/pilot_early_serial.c"
  60 #include "superio/serverengines/pilot/pilot_early_init.c"
  61 #include "superio/nsc/pc87417/pc87417_early_serial.c"
  62
  63 #include "cpu/x86/bist.h"
  64
  65 #include "northbridge/amd/amdk8/debug.c"
  66
  67 #include "cpu/x86/mtrr/earlymtrr.c"
  68
  69 #include "northbridge/amd/amdk8/setup_resource_map.c"
  70
  71 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
  72 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
  73
  74 #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
  75
  76 static void memreset(int controllers, const struct mem_controller *ctrl)
  77 {
  78 }
  79
  80 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  81 {
  82 #define SMBUS_SWITCH1 0x70
  83 #define SMBUS_SWITCH2 0x72
  84          unsigned device = (ctrl->channel0[0]) >> 8;
  85          smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
  86          smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
  87 }
  88
  89 static inline int spd_read_byte(unsigned device, unsigned address)
  90 {
  91          return smbus_read_byte(device, address);
  92 }
  93
  94 #include "northbridge/amd/amdk8/amdk8_f.h"
  95 #include "northbridge/amd/amdk8/incoherent_ht.c"
  96 #include "northbridge/amd/amdk8/coherent_ht.c"
  97 #include "northbridge/amd/amdk8/raminit_f.c"
  98 #include "lib/generic_sdram.c"
  99
 100 #include "cpu/amd/dualcore/dualcore.c"
 101
 102 //first node
 103 #define DIMM0 0x50
 104 #define DIMM1 0x51
 105 #define DIMM2 0x52
 106 #define DIMM3 0x53
 107 //second node
 108 #define DIMM4 0x54
 109 #define DIMM5 0x55
 110 #define DIMM6 0x56
 111 #define DIMM7 0x57
 112
 113
 114
 115 #include "cpu/amd/car/post_cache_as_ram.c"
 116
 117 #include "cpu/amd/model_fxx/init_cpus.c"
 118
 119 #include "cpu/amd/model_fxx/fidvid.c"
 120
 121 #include "northbridge/amd/amdk8/early_ht.c"
 122
 123 #if 0
 124 #include "ipmi.c"
 125
 126 static void setup_early_ipmi_serial()
 127 {
 128         unsigned char result;
 129         char channel_access[]={0x06<<2,0x40,0x04,0x80,0x05};
 130         char serialmodem_conf[]={0x0c<<2,0x10,0x04,0x08,0x00,0x0f};
 131         char serial_mux1[]={0x0c<<2,0x12,0x04,0x06};
 132         char serial_mux2[]={0x0c<<2,0x12,0x04,0x03};
 133         char serial_mux3[]={0x0c<<2,0x12,0x04,0x07};
 134
 135 //      earlydbg(0x0d);
 136         //set channel access system only
 137         ipmi_request(5,channel_access);
 138 //      earlydbg(result);
 139 /*
 140         //Set serial/modem config
 141         result=ipmi_request(6,serialmodem_conf);
 142         earlydbg(result);
 143
 144         //Set serial mux 1
 145         result=ipmi_request(4,serial_mux1);
 146         earlydbg(result);
 147
 148         //Set serial mux 2
 149         result=ipmi_request(4,serial_mux2);
 150         earlydbg(result);
 151
 152         //Set serial mux 3
 153         result=ipmi_request(4,serial_mux3);
 154         earlydbg(result);
 155 */
 156 //      earlydbg(0x0e);
 157
 158 }
 159 #endif
 160
 161 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 162 {
 163         static const uint16_t spd_addr[] = {
 164                 // first node
 165                  DIMM0, DIMM2, 0, 0,
 166                  DIMM1, DIMM3, 0, 0,
 167
 168                 // second node
 169                 DIMM4, DIMM6, 0, 0,
 170                 DIMM5, DIMM7, 0, 0,
 171         };
 172
 173         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 174                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 175
 176         int needs_reset;
 177         unsigned bsp_apicid = 0;
 178
 179         if (!cpu_init_detectedx && boot_cpu()) {
 180                 /* Nothing special needs to be done to find bus 0 */
 181                 /* Allow the HT devices to be found */
 182
 183                 enumerate_ht_chain();
 184                 bcm5785_enable_rom();
 185                 bcm5785_enable_lpc();
 186                 //enable RTC
 187                 pc87417_enable_dev(RTC_DEV);
 188         }
 189
 190         if (bist == 0) {
 191                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 192         }
 193
 194         pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 195
 196         uart_init();
 197
 198         /* Halt if there was a built in self test failure */
 199         report_bist_failure(bist);
 200
 201         console_init();
 202 //      setup_early_ipmi_serial();
 203         pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV
 204         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 205         printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
 206
 207 #if CONFIG_MEM_TRAIN_SEQ == 1
 208         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 209 #endif
 210         setup_coherent_ht_domain();
 211
 212         wait_all_core0_started();
 213 #if CONFIG_LOGICAL_CPUS==1
 214         // It is said that we should start core1 after all core0 launched
 215         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 216          * So here need to make sure last core0 is started, esp for two way system,
 217          * (there may be apic id conflicts in that case)
 218         */
 219         start_other_cores();
 220         wait_all_other_cores_started(bsp_apicid);
 221 #endif
 222
 223         /* it will set up chains and store link pair for optimization later */
 224         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 225         bcm5785_early_setup();
 226
 227 #if CONFIG_SET_FIDVID
 228         {
 229                 msr_t msr;
 230                 msr=rdmsr(0xc0010042);
 231                 printk(BIOS_DEBUG, "begin msr fid, vid %08x %08x\n", msr.hi, msr.lo);
 232         }
 233         enable_fid_change();
 234         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 235         init_fidvid_bsp(bsp_apicid);
 236         // show final fid and vid
 237         {
 238                 msr_t msr;
 239                 msr=rdmsr(0xc0010042);
 240                 printk(BIOS_DEBUG, "end msr fid, vid %08x %08x\n", msr.hi, msr.lo);
 241         }
 242 #endif
 243
 244         needs_reset = optimize_link_coherent_ht();
 245         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 246
 247         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 248         if (needs_reset) {
 249                 printk(BIOS_INFO, "ht reset -\n");
 250                 soft_reset();
 251         }
 252
 253         allow_all_aps_stop(bsp_apicid);
 254
 255         //It's the time to set ctrl in sysinfo now;
 256         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 257         enable_smbus();
 258
 259         //do we need apci timer, tsc...., only debug need it for better output
 260         /* all ap stopped? */
 261         // init_timer(); // Need to use TMICT to synconize FID/VID
 262
 263         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 264
 265         post_cache_as_ram();
 266 }
 267