2 * This file is part of the coreboot project.
4 * Copyright (C) 2001 Eric W.Biederman<ebiderman@lnxi.com>
6 * Copyright (C) 2006 AMD
7 * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
9 * Copyright (C) 2007 University of Mannheim
10 * Written by Philipp Degler <pdegler@rumms.uni-mannheim.e> for Uni of Mannheim
12 * Copyright (C) 2009 University of Heidelberg
13 * Written by Mondrian Nuessle <nuessle@uni-hd.de> for Uni of Heidelberg
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 #include <console/console.h>
31 #include <arch/smp/mpspec.h>
33 #include <device/pci.h>
36 #if CONFIG_LOGICAL_CPUS==1
37 #include <cpu/amd/multicore.h>
39 #include <cpu/amd/amdk8_sysconf.h>
40 #include "mb_sysconf.h"
42 static void *smp_write_config_table(void *v)
44 struct mp_config_table *mc;
45 struct mb_sysconf_t *m;
48 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
50 mptable_init(mc, "TREX ", LAPIC_ADDR);
52 smp_write_processors(mc);
57 mptable_write_buses(mc, NULL, &bus_isa);
59 /*I/O APICs: APIC ID Version State Address*/
65 dev = dev_find_device(0x1166, 0x0235, dev);
67 res = find_resource(dev, PCI_BASE_ADDRESS_0);
69 printk(BIOS_DEBUG, "APIC %d base address: %llx\n",m->apicid_bcm5785[i], res->base);
70 smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base);
77 /* IRQ routing as factory BIOS */
78 outb(0x01, 0xc00); outb(0x0A, 0xc01);
79 outb(0x17, 0xc00); outb(0x05, 0xc01);
80 /* outb(0x2E, 0xc00); outb(0x0B, 0xc01); */
81 /* outb(0x07, 0xc00); outb(0x07, 0xc01); */
82 outb(0x07, 0xc00); outb(0x0b, 0xc01);
84 outb(0x24, 0xc00); outb(0x05, 0xc01);
85 //outb(0x00, 0xc00); outb(0x09, 0xc01);
86 outb(0x02, 0xc00); outb(0x0E, 0xc01);
94 dev = dev_find_device(0x1166, 0x0205, 0);
97 dword = pci_read_config32(dev, 0x64);
98 dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7
99 pci_write_config32(dev, 0x64, dword);
101 // set GEVENT pins to NO OP
102 outb(0x33, 0xcd6); outb(0x00, 0xcd7);
103 outb(0x34, 0xcd6); outb(0x00, 0xcd7);
104 outb(0x35, 0xcd6); outb(0x00, 0xcd7);
107 // hide XIOAPIC PCI configuration space
110 dev = dev_find_device(0x1166, 0x205, 0);
113 dword = pci_read_config32(dev, 0x64);
115 pci_write_config32(dev, 0x64, dword);
119 mptable_add_isa_interrupts(mc, bus_isa, m->apicid_bcm5785[0], 0);
122 /* printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */
123 /* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */
124 printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb);
125 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb);
127 printk(BIOS_DEBUG, "sysconf.sbdn: %d on bus: %x \n",sysconf.sbdn, m->bus_bcm5785_0);
128 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x03<<2)|0, m->apicid_bcm5785[0], 0xa);
131 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x4<<2)|0, m->apicid_bcm5785[1], 0x7);
134 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6<<2)|0, m->apicid_bcm5785[2], 0xe);
135 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7<<2)|0, m->apicid_bcm5785[2], 0xe);
136 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8<<2)|0, m->apicid_bcm5785[2], 0xe);
137 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9<<2)|0, m->apicid_bcm5785[2], 0xe);
138 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa<<2)|0, m->apicid_bcm5785[2], 0xe);
141 // outb(0x02, 0xc00); outb(0x0e, 0xc01);
142 // printk(BIOS_DEBUG, "MPTABLE_IDE: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe);
143 // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, (0x02<<2)|1, m->apicid_bcm5785[0], 0xe);
145 //onboard Broadcom GbE
146 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4<<2)|0, m->apicid_bcm5785[2], 0x4);
147 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4<<2)|1, m->apicid_bcm5785[2], 0x4);
152 /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
155 dev = dev_find_device(0x1166, 0x0205, 0);
158 dword = pci_read_config32(dev, 0x6c);
159 dword |= (1<<4); // enable interrupts
160 printk(BIOS_DEBUG, "6ch: %x\n",dword);
161 pci_write_config32(dev, 0x6c, dword);
165 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
166 printk(BIOS_DEBUG, "bus_isa is: %x\n", bus_isa);
167 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
168 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa , 0x0, MP_APIC_ALL, 0x1);
170 //extended table entries
171 smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001);
172 smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x7f80, 0x0, 0x5e80);
173 smp_write_address_space(mc,0 , ADDRESS_TYPE_PREFETCH, 0x0, 0xde00, 0x0, 0x0100);
174 smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0xdf00, 0x0, 0x1fe0);
175 smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x1000, 0xfee0, 0xf000, 0x011f);
176 smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x000a, 0x0, 0x0006);
177 smp_write_bus_hierarchy(mc, 9, 0x01, 0);
178 smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 0);
179 smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 1);
182 /* Compute the checksums */
183 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
184 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
185 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
186 mc, smp_next_mpe_entry(mc));
187 return smp_next_mpe_entry(mc);
190 unsigned long write_smp_table(unsigned long addr)
193 v = smp_write_floating_table(addr);
194 return (unsigned long)smp_write_config_table(v);