src/mainboard/hp/dl145_g3/mptable.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2001 Eric W.Biederman<ebiderman@lnxi.com>
   5  *
   6  * Copyright (C) 2006 AMD
   7  * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
   8  *
   9  * Copyright (C) 2007 University of Mannheim
  10  * Written by Philipp Degler <pdegler@rumms.uni-mannheim.e> for Uni of Mannheim
  11  *
  12  * Copyright (C) 2009 University of Heidelberg
  13  * Written by Mondrian Nuessle <nuessle@uni-hd.de> for Uni of Heidelberg
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  28  */
  29
  30 #include <console/console.h>
  31 #include <arch/smp/mpspec.h>
  32 #include <arch/io.h>
  33 #include <device/pci.h>
  34 #include <string.h>
  35 #include <stdint.h>
  36 #if CONFIG_LOGICAL_CPUS==1
  37 #include <cpu/amd/multicore.h>
  38 #endif
  39 #include <cpu/amd/amdk8_sysconf.h>
  40 #include "mb_sysconf.h"
  41
  42 static void *smp_write_config_table(void *v)
  43 {
  44         struct mp_config_table *mc;
  45         struct mb_sysconf_t *m;
  46         int bus_isa;
  47
  48         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  49
  50         mptable_init(mc, LAPIC_ADDR);
  51
  52         smp_write_processors(mc);
  53
  54         get_bus_conf();
  55         m = sysconf.mb;
  56
  57         mptable_write_buses(mc, NULL, &bus_isa);
  58
  59         /*I/O APICs:   APIC ID Version State           Address*/
  60         {
  61                 device_t dev = 0;
  62                 int i;
  63                 struct resource *res;
  64                 for(i=0; i<3; i++) {
  65                         dev = dev_find_device(0x1166, 0x0235, dev);
  66                         if (dev) {
  67                                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
  68                                 if (res) {
  69                                         printk(BIOS_DEBUG, "APIC %d base address: %llx\n",m->apicid_bcm5785[i],  res->base);
  70                                         smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base);
  71                                 }
  72                         }
  73                 }
  74
  75         }
  76
  77         /* IRQ routing as factory BIOS */
  78         outb(0x01, 0xc00); outb(0x0A, 0xc01);
  79         outb(0x17, 0xc00); outb(0x05, 0xc01);
  80 /*      outb(0x2E, 0xc00); outb(0x0B, 0xc01); */
  81 /*      outb(0x07, 0xc00); outb(0x07, 0xc01); */
  82         outb(0x07, 0xc00); outb(0x0b, 0xc01);
  83
  84         outb(0x24, 0xc00); outb(0x05, 0xc01);
  85         //outb(0x00, 0xc00); outb(0x09, 0xc01);
  86         outb(0x02, 0xc00); outb(0x0E, 0xc01);
  87
  88         // 8259 registers...
  89         outb(0xa0, 0x4d0);
  90         outb(0x0e, 0x4d1);
  91
  92         {
  93                 device_t dev;
  94                 dev = dev_find_device(0x1166, 0x0205, 0);
  95                 if(dev) {
  96                         uint32_t dword;
  97                         dword = pci_read_config32(dev, 0x64);
  98                         dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7
  99                         pci_write_config32(dev, 0x64, dword);
 100                 }
 101                 // set GEVENT pins to NO OP
 102                 outb(0x33, 0xcd6); outb(0x00, 0xcd7);
 103                 outb(0x34, 0xcd6); outb(0x00, 0xcd7);
 104                 outb(0x35, 0xcd6); outb(0x00, 0xcd7);
 105         }
 106
 107         // hide XIOAPIC PCI configuration space
 108         {
 109                 device_t dev;
 110                 dev = dev_find_device(0x1166, 0x205, 0);
 111                 if (dev) {
 112                         uint32_t dword;
 113                         dword = pci_read_config32(dev, 0x64);
 114                         dword |= (1<<26);
 115                         pci_write_config32(dev, 0x64, dword);
 116                 }
 117         }
 118
 119         mptable_add_isa_interrupts(mc, bus_isa, m->apicid_bcm5785[0], 0);
 120
 121         //SATA
 122 /*      printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */
 123 /*      smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */
 124         printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb);
 125         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb);
 126         //USB
 127         printk(BIOS_DEBUG, "sysconf.sbdn: %d on bus: %x \n",sysconf.sbdn, m->bus_bcm5785_0);
 128         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x03<<2)|0, m->apicid_bcm5785[0], 0xa);
 129
 130         //VGA
 131         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x4<<2)|0, m->apicid_bcm5785[1], 0x7);
 132
 133         //PCIE
 134         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6<<2)|0, m->apicid_bcm5785[2], 0xe);
 135         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7<<2)|0, m->apicid_bcm5785[2], 0xe);
 136         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8<<2)|0, m->apicid_bcm5785[2], 0xe);
 137         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9<<2)|0, m->apicid_bcm5785[2], 0xe);
 138         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa<<2)|0, m->apicid_bcm5785[2], 0xe);
 139
 140         //IDE
 141 //      outb(0x02, 0xc00); outb(0x0e, 0xc01);
 142 //      printk(BIOS_DEBUG, "MPTABLE_IDE: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe);
 143 //              smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_bcm5785_0, (0x02<<2)|1, m->apicid_bcm5785[0], 0xe);
 144
 145         //onboard Broadcom GbE
 146         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4<<2)|0, m->apicid_bcm5785[2], 0x4);
 147         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4<<2)|1, m->apicid_bcm5785[2], 0x4);
 148
 149
 150
 151         /* enable int */
 152         /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
 153         {
 154                 device_t dev;
 155                 dev = dev_find_device(0x1166, 0x0205, 0);
 156                 if(dev) {
 157                         uint32_t dword;
 158                         dword = pci_read_config32(dev, 0x6c);
 159                         dword |= (1<<4); // enable interrupts
 160                         printk(BIOS_DEBUG, "6ch: %x\n",dword);
 161                         pci_write_config32(dev, 0x6c, dword);
 162                 }
 163         }
 164
 165 /*Local Ints:  Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#*/
 166         printk(BIOS_DEBUG, "bus_isa is: %x\n", bus_isa);
 167         mptable_lintsrc(mc, bus_isa);
 168
 169         //extended table entries
 170         smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001);
 171         smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x7f80, 0x0, 0x5e80);
 172         smp_write_address_space(mc,0 , ADDRESS_TYPE_PREFETCH, 0x0, 0xde00, 0x0, 0x0100);
 173         smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0xdf00, 0x0, 0x1fe0);
 174         smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x1000, 0xfee0, 0xf000, 0x011f);
 175         smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x000a, 0x0, 0x0006);
 176         smp_write_bus_hierarchy(mc, 9, 0x01, 0);
 177         smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 0);
 178         smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 1);
 179
 180
 181         /* Compute the checksums */
 182         return mptable_finalize(mc);
 183 }
 184
 185 unsigned long write_smp_table(unsigned long addr)
 186 {
 187         void *v;
 188         v = smp_write_floating_table(addr, 0);
 189         return (unsigned long)smp_write_config_table(v);
 190 }