src/mainboard/hp/dl145_g3/mptable.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2001 Eric W.Biederman<ebiderman@lnxi.com>
   5  *
   6  * Copyright (C) 2006 AMD
   7  * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
   8  *
   9  * Copyright (C) 2007 University of Mannheim
  10  * Written by Philipp Degler <pdegler@rumms.uni-mannheim.e> for Uni of Mannheim
  11  *
  12  * Copyright (C) 2009 University of Heidelberg
  13  * Written by Mondrian Nuessle <nuessle@uni-hd.de> for Uni of Heidelberg
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  28  */
  29
  30 #include <console/console.h>
  31 #include <arch/smp/mpspec.h>
  32 #include <arch/io.h>
  33 #include <device/pci.h>
  34 #include <string.h>
  35 #include <stdint.h>
  36 #if CONFIG_LOGICAL_CPUS==1
  37 #include <cpu/amd/multicore.h>
  38 #endif
  39 #include <cpu/amd/amdk8_sysconf.h>
  40 #include "mb_sysconf.h"
  41
  42 static void *smp_write_config_table(void *v)
  43 {
  44         struct mp_config_table *mc;
  45         struct mb_sysconf_t *m;
  46
  47         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  48
  49         mptable_init(mc, "TREX        ", LAPIC_ADDR);
  50
  51         smp_write_processors(mc);
  52
  53         get_bus_conf();
  54         m = sysconf.mb;
  55
  56         /*Bus:         Bus ID  Type*/
  57         /* define bus and isa numbers */
  58 #if 0
  59         unsigned char bus_num;
  60         for(bus_num = 0; bus_num < m->bus_isa; bus_num++) {
  61                 smp_write_bus(mc, bus_num, "PCI   ");
  62                 printk(BIOS_DEBUG, "writing bus %d as PCI...\n",bus_num);
  63         }
  64 #endif
  65         smp_write_bus(mc, 0, "PCI   ");
  66         smp_write_bus(mc, 1, "PCI   ");
  67         smp_write_bus(mc, 7, "PCI   ");
  68         smp_write_bus(mc, 8, "PCI   ");
  69
  70         smp_write_bus(mc,m->bus_isa, "ISA   ");
  71         printk(BIOS_DEBUG, "writing %d as ISA...\n",m->bus_isa);
  72
  73         /*I/O APICs:   APIC ID Version State           Address*/
  74         {
  75                 device_t dev = 0;
  76                 int i;
  77                 struct resource *res;
  78                 for(i=0; i<3; i++) {
  79                         dev = dev_find_device(0x1166, 0x0235, dev);
  80                         if (dev) {
  81                                 res = find_resource(dev, PCI_BASE_ADDRESS_0);
  82                                 if (res) {
  83                                         printk(BIOS_DEBUG, "APIC %d base address: %llx\n",m->apicid_bcm5785[i],  res->base);
  84                                         smp_write_ioapic(mc, m->apicid_bcm5785[i], 0x11, res->base);
  85                                 }
  86                         }
  87                 }
  88
  89         }
  90
  91         /* IRQ routing as factory BIOS */
  92         outb(0x01, 0xc00); outb(0x0A, 0xc01);
  93         outb(0x17, 0xc00); outb(0x05, 0xc01);
  94 /*      outb(0x2E, 0xc00); outb(0x0B, 0xc01); */
  95 /*      outb(0x07, 0xc00); outb(0x07, 0xc01); */
  96         outb(0x07, 0xc00); outb(0x0b, 0xc01);
  97
  98         outb(0x24, 0xc00); outb(0x05, 0xc01);
  99         //outb(0x00, 0xc00); outb(0x09, 0xc01);
 100         outb(0x02, 0xc00); outb(0x0E, 0xc01);
 101
 102         // 8259 registers...
 103         outb(0xa0, 0x4d0);
 104         outb(0x0e, 0x4d1);
 105
 106         {
 107                 device_t dev;
 108                 dev = dev_find_device(0x1166, 0x0205, 0);
 109                 if(dev) {
 110                         uint32_t dword;
 111                         dword = pci_read_config32(dev, 0x64);
 112                         dword |= (1<<30); // GEVENT14-21 used as PCI IRQ0-7
 113                         pci_write_config32(dev, 0x64, dword);
 114                 }
 115                 // set GEVENT pins to NO OP
 116                 outb(0x33, 0xcd6); outb(0x00, 0xcd7);
 117                 outb(0x34, 0xcd6); outb(0x00, 0xcd7);
 118                 outb(0x35, 0xcd6); outb(0x00, 0xcd7);
 119         }
 120
 121         // hide XIOAPIC PCI configuration space
 122         {
 123                 device_t dev;
 124                 dev = dev_find_device(0x1166, 0x205, 0);
 125                 if (dev) {
 126                         uint32_t dword;
 127                         dword = pci_read_config32(dev, 0x64);
 128                         dword |= (1<<26);
 129                         pci_write_config32(dev, 0x64, dword);
 130                 }
 131         }
 132
 133         mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_bcm5785[0], 0);
 134
 135         //SATA
 136 /*      printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */
 137 /*      smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */
 138         printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb);
 139         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb);
 140         //USB
 141         printk(BIOS_DEBUG, "sysconf.sbdn: %d on bus: %x \n",sysconf.sbdn, m->bus_bcm5785_0);
 142         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x03<<2)|0, m->apicid_bcm5785[0], 0xa);
 143
 144         //VGA
 145         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x4<<2)|0, m->apicid_bcm5785[1], 0x7);
 146
 147         //PCIE
 148         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6<<2)|0, m->apicid_bcm5785[2], 0xe);
 149         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7<<2)|0, m->apicid_bcm5785[2], 0xe);
 150         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8<<2)|0, m->apicid_bcm5785[2], 0xe);
 151         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9<<2)|0, m->apicid_bcm5785[2], 0xe);
 152         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa<<2)|0, m->apicid_bcm5785[2], 0xe);
 153
 154         //IDE
 155 //      outb(0x02, 0xc00); outb(0x0e, 0xc01);
 156 //      printk(BIOS_DEBUG, "MPTABLE_IDE: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe);
 157 //              smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  m->bus_bcm5785_0, (0x02<<2)|1, m->apicid_bcm5785[0], 0xe);
 158
 159         //onboard Broadcom GbE
 160         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4<<2)|0, m->apicid_bcm5785[2], 0x4);
 161         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4<<2)|1, m->apicid_bcm5785[2], 0x4);
 162
 163
 164
 165         /* enable int */
 166         /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
 167         {
 168                 device_t dev;
 169                 dev = dev_find_device(0x1166, 0x0205, 0);
 170                 if(dev) {
 171                         uint32_t dword;
 172                         dword = pci_read_config32(dev, 0x6c);
 173                         dword |= (1<<4); // enable interrupts
 174                         printk(BIOS_DEBUG, "6ch: %x\n",dword);
 175                         pci_write_config32(dev, 0x6c, dword);
 176                 }
 177         }
 178
 179 /*Local Ints:  Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#*/
 180         printk(BIOS_DEBUG, "m->bus_isa is: %x\n",m->bus_isa);
 181         smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
 182         smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa , 0x0, MP_APIC_ALL, 0x1);
 183
 184         //extended table entries
 185         smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001);
 186         smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x7f80, 0x0, 0x5e80);
 187         smp_write_address_space(mc,0 , ADDRESS_TYPE_PREFETCH, 0x0, 0xde00, 0x0, 0x0100);
 188         smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0xdf00, 0x0, 0x1fe0);
 189         smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x1000, 0xfee0, 0xf000, 0x011f);
 190         smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x000a, 0x0, 0x0006);
 191         smp_write_bus_hierarchy(mc, 9, 0x01, 0);
 192         smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 0);
 193         smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 1);
 194
 195
 196         /* Compute the checksums */
 197         mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 198         mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 199         printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 200                 mc, smp_next_mpe_entry(mc));
 201         return smp_next_mpe_entry(mc);
 202 }
 203
 204 unsigned long write_smp_table(unsigned long addr)
 205 {
 206         void *v;
 207         v = smp_write_floating_table(addr);
 208         return (unsigned long)smp_write_config_table(v);
 209 }