src/mainboard/hp/dl145_g3/cache_as_ram_auto.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 Tyan
   5  * Copyright (C) 2006 AMD
   6  * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD.
   7  *
   8  * Copyright (C) 2007 University of Mannheim
   9  * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim
  10  * Copyright (C) 2009 University of Heidelberg
  11  * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  26  */
  27
  28 #define ASSEMBLY 1
  29 #define __ROMCC__
  30
  31 #define RAMINIT_SYSINFO 1
  32
  33 #define K8_ALLOCATE_IO_RANGE 1
  34 //#define K8_SCAN_PCI_BUS 1
  35
  36 #define QRANK_DIMM_SUPPORT 1
  37
  38 #if CONFIG_LOGICAL_CPUS==1
  39 #define SET_NB_CFG_54 1
  40 #endif
  41
  42 //used by init_cpus and fidvid
  43 #define K8_SET_FIDVID 1
  44 //if we want to wait for core1 done before DQS training, set it to 0
  45 #define K8_SET_FIDVID_CORE0_ONLY 1
  46
  47 #if K8_REV_F_SUPPORT == 1
  48 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  49 #endif
  50
  51 #define DBGP_DEFAULT 7
  52
  53 #include <stdint.h>
  54 #include <string.h>
  55 #include <device/pci_def.h>
  56 #include <device/pci_ids.h>
  57 #include <arch/io.h>
  58 #include <device/pnp_def.h>
  59 #include <arch/romcc_io.h>
  60 #include <cpu/x86/lapic.h>
  61 #include "option_table.h"
  62 #include "pc80/mc146818rtc_early.c"
  63
  64
  65 #if USE_FAILOVER_IMAGE==0
  66 #include "pc80/serial.c"
  67 #include "arch/i386/lib/console.c"
  68 #include "ram/ramtest.c"
  69
  70 #include <cpu/amd/model_fxx_rev.h>
  71
  72 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
  73 #include "northbridge/amd/amdk8/raminit.h"
  74 #include "cpu/amd/model_fxx/apic_timer.c"
  75 #include "lib/delay.c"
  76
  77 #endif
  78
  79 #include "cpu/x86/lapic/boot_cpu.c"
  80 #include "northbridge/amd/amdk8/reset_test.c"
  81
  82 #include "superio/serverengines/pilot/pilot_early_serial.c"
  83 #include "superio/serverengines/pilot/pilot_early_init.c"
  84 #include "superio/nsc/pc87417/pc87417_early_serial.c"
  85
  86
  87 #if USE_FAILOVER_IMAGE==0
  88
  89 #include "cpu/x86/bist.h"
  90
  91 #include "northbridge/amd/amdk8/debug.c"
  92
  93 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  94
  95 #include "northbridge/amd/amdk8/setup_resource_map.c"
  96
  97 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
  98 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
  99
 100 #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
 101
 102 static void memreset_setup(void)
 103 {
 104 }
 105
 106 static void memreset(int controllers, const struct mem_controller *ctrl)
 107 {
 108 }
 109
 110 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 111 {
 112 #define SMBUS_SWITCH1 0x70
 113 #define SMBUS_SWITCH2 0x72
 114          unsigned device = (ctrl->channel0[0]) >> 8;
 115          smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
 116          smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
 117 }
 118
 119 static inline int spd_read_byte(unsigned device, unsigned address)
 120 {
 121          return smbus_read_byte(device, address);
 122 }
 123
 124 #include "northbridge/amd/amdk8/amdk8_f.h"
 125 #include "northbridge/amd/amdk8/coherent_ht.c"
 126
 127 #include "northbridge/amd/amdk8/incoherent_ht.c"
 128
 129 #include "northbridge/amd/amdk8/raminit_f.c"
 130
 131 #include "sdram/generic_sdram.c"
 132
 133 //#include "resourcemap.c"
 134
 135 #include "cpu/amd/dualcore/dualcore.c"
 136
 137 //first node
 138 #define DIMM0 0x50
 139 #define DIMM1 0x51
 140 #define DIMM2 0x52
 141 #define DIMM3 0x53
 142 //second node
 143 #define DIMM4 0x54
 144 #define DIMM5 0x55
 145 #define DIMM6 0x56
 146 #define DIMM7 0x57
 147
 148
 149 #include "cpu/amd/car/copy_and_run.c"
 150
 151 #include "cpu/amd/car/post_cache_as_ram.c"
 152
 153 #include "cpu/amd/model_fxx/init_cpus.c"
 154
 155 #include "cpu/amd/model_fxx/fidvid.c"
 156
 157 #endif
 158
 159 #if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
 160
 161 #include "northbridge/amd/amdk8/early_ht.c"
 162
 163 #if 0
 164 #include "ipmi.c"
 165
 166 static void setup_early_ipmi_serial()
 167 {
 168         unsigned char result;
 169         char channel_access[]={0x06<<2,0x40,0x04,0x80,0x05};
 170         char serialmodem_conf[]={0x0c<<2,0x10,0x04,0x08,0x00,0x0f};
 171         char serial_mux1[]={0x0c<<2,0x12,0x04,0x06};
 172         char serial_mux2[]={0x0c<<2,0x12,0x04,0x03};
 173         char serial_mux3[]={0x0c<<2,0x12,0x04,0x07};
 174
 175 //      earlydbg(0x0d);
 176         //set channel access system only
 177         ipmi_request(5,channel_access);
 178 //      earlydbg(result);
 179 /*
 180         //Set serial/modem config
 181         result=ipmi_request(6,serialmodem_conf);
 182         earlydbg(result);
 183
 184         //Set serial mux 1
 185         result=ipmi_request(4,serial_mux1);
 186         earlydbg(result);
 187
 188         //Set serial mux 2
 189         result=ipmi_request(4,serial_mux2);
 190         earlydbg(result);
 191
 192         //Set serial mux 3
 193         result=ipmi_request(4,serial_mux3);
 194         earlydbg(result);
 195 */
 196 //      earlydbg(0x0e);
 197
 198 }
 199 #endif
 200
 201
 202 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 203 {
 204          /* Is this a cpu only reset? Is this a secondary cpu? */
 205          if ((cpu_init_detectedx) || (!boot_cpu())) {
 206                 if (last_boot_normal()) { // RTC already inited
 207                         goto normal_image; //normal_image;
 208                 } else {
 209                         goto fallback_image;
 210                 }
 211          }
 212
 213          /* Nothing special needs to be done to find bus 0 */
 214          /* Allow the HT devices to be found */
 215
 216          enumerate_ht_chain();
 217          bcm5785_enable_rom();
 218          bcm5785_enable_lpc();
 219          //enable RTC
 220         pc87417_enable_dev(RTC_DEV);
 221
 222          /* Is this a deliberate reset by the bios */
 223
 224          if (bios_reset_detected() && last_boot_normal()) {
 225                 goto normal_image;
 226          }
 227          /* This is the primary cpu how should I boot? */
 228          else if (do_normal_boot()) {
 229                 goto normal_image;
 230          }
 231          else {
 232                 goto fallback_image;
 233          }
 234  normal_image:
 235          __asm__ volatile ("jmp __normal_image"
 236                 : /* outputs */
 237                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 238                 );
 239
 240  fallback_image:
 241 #if HAVE_FAILOVER_BOOT==1
 242         __asm__ volatile ("jmp __fallback_image"
 243                 : /* outputs */
 244                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 245                 )
 246 #endif
 247          ;
 248
 249 }
 250 #endif
 251
 252 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 253
 254 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 255 {
 256 #if HAVE_FAILOVER_BOOT==1
 257     #if USE_FAILOVER_IMAGE==1
 258         failover_process(bist, cpu_init_detectedx);
 259     #else
 260         real_main(bist, cpu_init_detectedx);
 261     #endif
 262 #else
 263     #if USE_FALLBACK_IMAGE == 1
 264         failover_process(bist, cpu_init_detectedx);
 265     #endif
 266         real_main(bist, cpu_init_detectedx);
 267 #endif
 268 }
 269
 270 #if USE_FAILOVER_IMAGE==0
 271
 272 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 273 {
 274         static const uint16_t spd_addr[] = {
 275                 //first node
 276                  DIMM0, DIMM2, 0, 0,
 277                  DIMM1, DIMM3, 0, 0,
 278 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 279                 //second node
 280                 DIMM4, DIMM6, 0, 0,
 281                 DIMM5, DIMM7, 0, 0,
 282 #endif
 283
 284         };
 285
 286         struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
 287
 288          int needs_reset;
 289          unsigned bsp_apicid = 0;
 290
 291
 292          if (bist == 0) {
 293                  bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 294          }
 295
 296         pilot_enable_serial(SERIAL_DEV, TTYS0_BASE);
 297
 298         //setup_mp_resource_map();
 299
 300         uart_init();
 301
 302         /* Halt if there was a built in self test failure */
 303         report_bist_failure(bist);
 304
 305
 306         console_init();
 307 //      setup_early_ipmi_serial();
 308         pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV
 309         print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
 310
 311         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 312
 313 #if MEM_TRAIN_SEQ == 1
 314         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 315 #endif
 316         setup_coherent_ht_domain();
 317
 318         wait_all_core0_started();
 319 #if CONFIG_LOGICAL_CPUS==1
 320         // It is said that we should start core1 after all core0 launched
 321         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 322          * So here need to make sure last core0 is started, esp for two way system,
 323          * (there may be apic id conflicts in that case)
 324         */
 325         start_other_cores();
 326         wait_all_other_cores_started(bsp_apicid);
 327 #endif
 328
 329         /* it will set up chains and store link pair for optimization later */
 330         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 331         bcm5785_early_setup();
 332
 333 #if K8_SET_FIDVID == 1
 334         {
 335                 msr_t msr;
 336                 msr=rdmsr(0xc0010042);
 337                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 338         }
 339         enable_fid_change();
 340         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 341         init_fidvid_bsp(bsp_apicid);
 342         // show final fid and vid
 343         {
 344                 msr_t msr;
 345                 msr=rdmsr(0xc0010042);
 346                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 347         }
 348 #endif
 349
 350         needs_reset = optimize_link_coherent_ht();
 351         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 352
 353         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 354         if (needs_reset) {
 355                 print_info("ht reset -\r\n");
 356                 soft_reset();
 357         }
 358
 359         allow_all_aps_stop(bsp_apicid);
 360
 361         //It's the time to set ctrl in sysinfo now;
 362         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 363         enable_smbus();
 364
 365         memreset_setup();
 366         //do we need apci timer, tsc...., only debug need it for better output
 367         /* all ap stopped? */
 368 //      init_timer(); // Need to use TMICT to synconize FID/VID
 369
 370         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 371
 372         post_cache_as_ram();
 373
 374 }
 375
 376 #endif