broadcom/bcm5785: Move HAVE_HARD_RESET to southbridge
[coreboot.git] / src / mainboard / hp / dl145_g3 / Kconfig
1 if BOARD_HP_DL145_G3
2
3 config BOARD_SPECIFIC_OPTIONS # dummy
4         def_bool y
5         select ARCH_X86
6         select CPU_AMD_SOCKET_F
7         select DIMM_DDR2
8         select DIMM_REGISTERED
9         select NORTHBRIDGE_AMD_AMDK8
10         select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
11         select SOUTHBRIDGE_BROADCOM_BCM21000
12         select SOUTHBRIDGE_BROADCOM_BCM5785
13         select SUPERIO_NSC_PC87417
14         select HAVE_BUS_CONFIG
15         select HAVE_OPTION_TABLE
16         select HAVE_PIRQ_TABLE
17         select HAVE_MP_TABLE
18         select LIFT_BSP_APIC_ID
19         select BOARD_ROMSIZE_KB_512
20         select RAMINIT_SYSINFO
21         select SB_HT_CHAIN_UNITID_OFFSET_ONLY
22         select QRANK_DIMM_SUPPORT
23         select K8_ALLOCATE_IO_RANGE
24         select SET_FIDVID
25
26 config MAINBOARD_DIR
27         string
28         default hp/dl145_g3
29
30 config DCACHE_RAM_BASE
31         hex
32         default 0xcc000
33
34 config DCACHE_RAM_SIZE
35         hex
36         default 0x04000
37
38 config DCACHE_RAM_GLOBAL_VAR_SIZE
39         hex
40         default 0x01000
41
42 config APIC_ID_OFFSET
43         hex
44         default 0x8
45
46 config SB_HT_CHAIN_ON_BUS0
47         int
48         default 2
49
50 config MAINBOARD_PART_NUMBER
51         string
52         default "ProLiant DL145 G3"
53
54 config MAX_CPUS
55         int
56         default 4
57
58 config MAX_PHYSICAL_CPUS
59         int
60         default 2
61
62 config HT_CHAIN_END_UNITID_BASE
63         hex
64         default 0x1
65
66 config HT_CHAIN_UNITID_BASE
67         hex
68         default 0x6
69
70 config SB_HT_CHAIN_ON_BUS0
71         int
72         default 2
73
74 config IRQ_SLOT_COUNT
75         int
76         default 15
77
78 endif # BOARD_HP_DL145_G3