Move "select CACHE_AS_RAM" lines from boards into CPU socket.
[coreboot.git] / src / mainboard / hp / dl145_g3 / Kconfig
1 if BOARD_HP_DL145_G3
2
3 config BOARD_SPECIFIC_OPTIONS # dummy
4         def_bool y
5         select ARCH_X86
6         select CPU_AMD_SOCKET_F
7         select DIMM_DDR2
8         select DIMM_REGISTERED
9         select NORTHBRIDGE_AMD_AMDK8
10         select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
11         select SOUTHBRIDGE_BROADCOM_BCM21000
12         select SOUTHBRIDGE_BROADCOM_BCM5785
13         select SUPERIO_NSC_PC87417
14         select HAVE_BUS_CONFIG
15         select HAVE_OPTION_TABLE
16         select HAVE_PIRQ_TABLE
17         select HAVE_MP_TABLE
18         select HAVE_HARD_RESET
19         select LIFT_BSP_APIC_ID
20         select BOARD_ROMSIZE_KB_512
21         select RAMINIT_SYSINFO
22         select SB_HT_CHAIN_UNITID_OFFSET_ONLY
23         select QRANK_DIMM_SUPPORT
24         select K8_ALLOCATE_IO_RANGE
25         select SET_FIDVID
26
27 config MAINBOARD_DIR
28         string
29         default hp/dl145_g3
30
31 config DCACHE_RAM_BASE
32         hex
33         default 0xcc000
34
35 config DCACHE_RAM_SIZE
36         hex
37         default 0x04000
38
39 config DCACHE_RAM_GLOBAL_VAR_SIZE
40         hex
41         default 0x01000
42
43 config APIC_ID_OFFSET
44         hex
45         default 0x8
46
47 config SB_HT_CHAIN_ON_BUS0
48         int
49         default 2
50
51 config MAINBOARD_PART_NUMBER
52         string
53         default "ProLiant DL145 G3"
54
55 config MAX_CPUS
56         int
57         default 4
58
59 config MAX_PHYSICAL_CPUS
60         int
61         default 2
62
63 config HT_CHAIN_END_UNITID_BASE
64         hex
65         default 0x1
66
67 config HT_CHAIN_UNITID_BASE
68         hex
69         default 0x6
70
71 config SB_HT_CHAIN_ON_BUS0
72         int
73         default 2
74
75 config IRQ_SLOT_COUNT
76         int
77         default 15
78
79 endif # BOARD_HP_DL145_G3