src/mainboard/hp/dl145_g1/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10
  11 #include <cpu/amd/model_fxx_rev.h>
  12
  13 #include "northbridge/amd/amdk8/incoherent_ht.c"
  14 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  15 #include "northbridge/amd/amdk8/raminit.h"
  16 #include "cpu/amd/model_fxx/apic_timer.c"
  17 #include "lib/delay.c"
  18
  19 #include "cpu/x86/lapic/boot_cpu.c"
  20 #include "northbridge/amd/amdk8/reset_test.c"
  21 #include "northbridge/amd/amdk8/debug.c"
  22 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  23
  24 #include "cpu/x86/mtrr/earlymtrr.c"
  25 #include "cpu/x86/bist.h"
  26
  27 #include "northbridge/amd/amdk8/setup_resource_map.c"
  28
  29 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  30
  31 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  32
  33 static void memreset_setup(void)
  34 {
  35    if (is_cpu_pre_c0()) {
  36       /* Set the memreset low */
  37       outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
  38       /* Ensure the BIOS has control of the memory lines */
  39       outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  40    } else {
  41       /* Ensure the CPU has controll of the memory lines */
  42       outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
  43    }
  44 }
  45
  46 static void memreset(int controllers, const struct mem_controller *ctrl)
  47 {
  48    if (is_cpu_pre_c0()) {
  49       udelay(800);
  50       /* Set memreset_high */
  51       outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
  52       udelay(90);
  53    }
  54 }
  55
  56 #define SMBUS_HUB 0x18
  57
  58 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  59 {
  60   int ret,i;
  61   unsigned device=(ctrl->channel0[0])>>8;
  62   /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
  63   i=2;
  64   do {
  65     ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  66   } while ((ret!=0) && (i-->0));
  67
  68   smbus_write_byte(SMBUS_HUB, 0x03, 0);
  69 }
  70
  71 static inline void change_i2c_mux(unsigned device)
  72 {
  73   int ret, i;
  74   print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  75   i=2;
  76   do {
  77     ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  78     print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
  79   } while ((ret!=0) && (i-->0));
  80   ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
  81   print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
  82 }
  83
  84 static inline int spd_read_byte(unsigned device, unsigned address)
  85 {
  86         return smbus_read_byte(device, address);
  87 }
  88
  89 #include "northbridge/amd/amdk8/raminit.c"
  90 #include "resourcemap.c"
  91 #include "northbridge/amd/amdk8/coherent_ht.c"
  92 #include "lib/generic_sdram.c"
  93
  94 #include "cpu/amd/dualcore/dualcore.c"
  95 #include <spd.h>
  96
  97 #define RC0 ((1<<1)<<8) // Not sure about these values
  98 #define RC1 ((1<<2)<<8) // Not sure about these values
  99
 100 #include "cpu/amd/car/post_cache_as_ram.c"
 101
 102 #include "cpu/amd/model_fxx/init_cpus.c"
 103
 104 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 105 #include "northbridge/amd/amdk8/early_ht.c"
 106
 107
 108 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 109 {
 110         static const uint16_t spd_addr [] = {
 111                         //first node
 112                         RC0|DIMM0, RC0|DIMM2, 0, 0,
 113                         RC0|DIMM1, RC0|DIMM3, 0, 0,
 114 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 115                         //second node
 116                         RC1|DIMM0, RC1|DIMM2, 0, 0,
 117                         RC1|DIMM1, RC1|DIMM3, 0, 0,
 118 #endif
 119         };
 120
 121         int needs_reset;
 122         unsigned bsp_apicid = 0;
 123
 124         struct mem_controller ctrl[8];
 125         unsigned nodes;
 126
 127         if (!cpu_init_detectedx && boot_cpu()) {
 128                 /* Nothing special needs to be done to find bus 0 */
 129                 /* Allow the HT devices to be found */
 130
 131                 enumerate_ht_chain();
 132
 133                 /* Setup the amd8111 */
 134                 amd8111_enable_rom();
 135         }
 136
 137         if (bist == 0) {
 138                 bsp_apicid = init_cpus(cpu_init_detectedx);
 139         }
 140
 141 //      post_code(0x32);
 142
 143         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 144         uart_init();
 145         console_init();
 146
 147         /* Halt if there was a built in self test failure */
 148         report_bist_failure(bist);
 149
 150         setup_dl145g1_resource_map();
 151         //setup_default_resource_map();
 152
 153         needs_reset = setup_coherent_ht_domain();
 154
 155         wait_all_core0_started();
 156 #if CONFIG_LOGICAL_CPUS==1
 157         // It is said that we should start core1 after all core0 launched
 158         start_other_cores();
 159         wait_all_other_cores_started(bsp_apicid);
 160 #endif
 161
 162         needs_reset |= ht_setup_chains_x();
 163
 164         if (needs_reset) {
 165                 print_info("ht reset -\n");
 166                 soft_reset();
 167         }
 168
 169         enable_smbus();
 170
 171         int i;
 172         for(i=0;i<2;i++) {
 173                 activate_spd_rom(&ctrl[i]);
 174         }
 175         for(i=2;i<8;i<<=1) {
 176                 change_i2c_mux(i);
 177         }
 178
 179         //dump_spd_registers(&ctrl[0]);
 180         //dump_spd_registers(&ctrl[1]);
 181         //dump_smbus_registers();
 182
 183         allow_all_aps_stop(bsp_apicid);
 184
 185         nodes = get_nodes();
 186         //It's the time to set ctrl now;
 187         fill_mem_ctrl(nodes, ctrl, spd_addr);
 188
 189         memreset_setup();
 190         sdram_initialize(nodes, ctrl);
 191
 192         //dump_pci_devices();
 193
 194         post_cache_as_ram();
 195 }