src/mainboard/hp/dl145_g1/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <device/pci_ids.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10 #include <cpu/amd/model_fxx_rev.h>
  11 #include "northbridge/amd/amdk8/amdk8.h"
  12 #include "southbridge/amd/amd8111/early_smbus.c"
  13 #include "northbridge/amd/amdk8/raminit.h"
  14 #include "cpu/amd/model_fxx/apic_timer.c"
  15 #include "northbridge/amd/amdk8/reset_test.c"
  16 #include "northbridge/amd/amdk8/debug.c"
  17 #include "superio/winbond/w83627hf/early_serial.c"
  18 #include "cpu/x86/mtrr/earlymtrr.c"
  19 #include "cpu/x86/bist.h"
  20 #include "southbridge/amd/amd8111/early_ctrl.c"
  21
  22 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  23
  24 static void memreset_setup(void)
  25 {
  26    if (is_cpu_pre_c0()) {
  27       /* Set the memreset low. */
  28       outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
  29       /* Ensure the BIOS has control of the memory lines. */
  30       outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  31    } else {
  32       /* Ensure the CPU has control of the memory lines. */
  33       outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
  34    }
  35 }
  36
  37 static void memreset(int controllers, const struct mem_controller *ctrl)
  38 {
  39    if (is_cpu_pre_c0()) {
  40       udelay(800);
  41       /* Set memreset high. */
  42       outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
  43       udelay(90);
  44    }
  45 }
  46
  47 #define SMBUS_HUB 0x18
  48
  49 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  50 {
  51   int ret,i;
  52   unsigned device=(ctrl->channel0[0])>>8;
  53   /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
  54   i=2;
  55   do {
  56     ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  57   } while ((ret!=0) && (i-->0));
  58   smbus_write_byte(SMBUS_HUB, 0x03, 0);
  59 }
  60
  61 static inline void change_i2c_mux(unsigned device)
  62 {
  63   int ret, i;
  64   print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  65   i=2;
  66   do {
  67     ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  68     print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
  69   } while ((ret!=0) && (i-->0));
  70   ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
  71   print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
  72 }
  73
  74 static inline int spd_read_byte(unsigned device, unsigned address)
  75 {
  76         return smbus_read_byte(device, address);
  77 }
  78
  79 #include "northbridge/amd/amdk8/incoherent_ht.c"
  80 #include "northbridge/amd/amdk8/raminit.c"
  81 #include "resourcemap.c"
  82 #include "northbridge/amd/amdk8/coherent_ht.c"
  83 #include "lib/generic_sdram.c"
  84 #include "cpu/amd/dualcore/dualcore.c"
  85 #include <spd.h>
  86 #include "cpu/amd/car/post_cache_as_ram.c"
  87 #include "cpu/amd/model_fxx/init_cpus.c"
  88
  89 #define RC0 ((1<<1)<<8)
  90 #define RC1 ((1<<2)<<8)
  91
  92 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  93 {
  94         static const uint16_t spd_addr [] = {
  95                 //first node
  96                 RC0|DIMM0, RC0|DIMM2, 0, 0,
  97                 RC0|DIMM1, RC0|DIMM3, 0, 0,
  98 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  99                 //second node
 100                 RC1|DIMM0, RC1|DIMM2, 0, 0,
 101                 RC1|DIMM1, RC1|DIMM3, 0, 0,
 102 #endif
 103         };
 104         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 105                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 106
 107         int needs_reset = 0;
 108         unsigned bsp_apicid = 0;
 109
 110         if (bist == 0)
 111                 bsp_apicid = init_cpus(cpu_init_detectedx,sysinfo);
 112
 113         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 114         console_init();
 115
 116         /* Halt if there was a built in self test failure */
 117         report_bist_failure(bist);
 118
 119         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 120
 121         setup_dl145g1_resource_map();
 122         //setup_default_resource_map();
 123
 124 #if CONFIG_MEM_TRAIN_SEQ == 1
 125         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 126 #endif
 127         setup_coherent_ht_domain();
 128         wait_all_core0_started();
 129 #if CONFIG_LOGICAL_CPUS==1
 130         // It is said that we should start core1 after all core0 launched
 131         start_other_cores();
 132         wait_all_other_cores_started(bsp_apicid);
 133 #endif
 134
 135         ht_setup_chains_x(sysinfo);
 136
 137         needs_reset |= optimize_link_coherent_ht();
 138         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 139
 140         if (needs_reset) {
 141                 print_info("ht reset -\n");
 142                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 143         }
 144
 145         enable_smbus();
 146
 147         int i;
 148         for(i=0;i<2;i++) {
 149                 activate_spd_rom(&sysinfo->ctrl[i]);
 150         }
 151         for(i=RC0;i<=RC1;i<<=1) {
 152                 change_i2c_mux(i);
 153         }
 154
 155         //dump_spd_registers(&sysinfo->ctrl[0]);
 156         //dump_spd_registers(&sysinfo->ctrl[1]);
 157         //dump_smbus_registers();
 158
 159         allow_all_aps_stop(bsp_apicid);
 160
 161         //It's the time to set ctrl now;
 162         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 163
 164         memreset_setup();
 165         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 166
 167         //dump_pci_devices();
 168
 169         post_cache_as_ram();
 170 }