src/mainboard/hp/dl145_g1/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10 #include <cpu/amd/model_fxx_rev.h>
  11 #include "northbridge/amd/amdk8/incoherent_ht.c"
  12 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  13 #include "northbridge/amd/amdk8/raminit.h"
  14 #include "cpu/amd/model_fxx/apic_timer.c"
  15 #include "lib/delay.c"
  16 #include "cpu/x86/lapic/boot_cpu.c"
  17 #include "northbridge/amd/amdk8/reset_test.c"
  18 #include "northbridge/amd/amdk8/debug.c"
  19 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  20 #include "cpu/x86/mtrr/earlymtrr.c"
  21 #include "cpu/x86/bist.h"
  22 #include "northbridge/amd/amdk8/setup_resource_map.c"
  23 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  24
  25 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  26
  27 static void memreset_setup(void)
  28 {
  29    if (is_cpu_pre_c0()) {
  30       /* Set the memreset low. */
  31       outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
  32       /* Ensure the BIOS has control of the memory lines. */
  33       outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  34    } else {
  35       /* Ensure the CPU has control of the memory lines. */
  36       outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
  37    }
  38 }
  39
  40 static void memreset(int controllers, const struct mem_controller *ctrl)
  41 {
  42    if (is_cpu_pre_c0()) {
  43       udelay(800);
  44       /* Set memreset high. */
  45       outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
  46       udelay(90);
  47    }
  48 }
  49
  50 #define SMBUS_HUB 0x18
  51
  52 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  53 {
  54   int ret,i;
  55   unsigned device=(ctrl->channel0[0])>>8;
  56   /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
  57   i=2;
  58   do {
  59     ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  60   } while ((ret!=0) && (i-->0));
  61
  62   smbus_write_byte(SMBUS_HUB, 0x03, 0);
  63 }
  64
  65 static inline void change_i2c_mux(unsigned device)
  66 {
  67   int ret, i;
  68   print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  69   i=2;
  70   do {
  71     ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  72     print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
  73   } while ((ret!=0) && (i-->0));
  74   ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
  75   print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
  76 }
  77
  78 static inline int spd_read_byte(unsigned device, unsigned address)
  79 {
  80         return smbus_read_byte(device, address);
  81 }
  82
  83 #include "northbridge/amd/amdk8/raminit.c"
  84 #include "resourcemap.c"
  85 #include "northbridge/amd/amdk8/coherent_ht.c"
  86 #include "lib/generic_sdram.c"
  87 #include "cpu/amd/dualcore/dualcore.c"
  88 #include <spd.h>
  89 #include "cpu/amd/car/post_cache_as_ram.c"
  90 #include "cpu/amd/model_fxx/init_cpus.c"
  91 #include "northbridge/amd/amdk8/early_ht.c"
  92
  93 #define RC0 ((1<<1)<<8) // Not sure about these values
  94 #define RC1 ((1<<2)<<8) // Not sure about these values
  95
  96 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  97 {
  98         static const uint16_t spd_addr [] = {
  99                 //first node
 100                 RC0|DIMM0, RC0|DIMM2, 0, 0,
 101                 RC0|DIMM1, RC0|DIMM3, 0, 0,
 102 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 103                 //second node
 104                 RC1|DIMM0, RC1|DIMM2, 0, 0,
 105                 RC1|DIMM1, RC1|DIMM3, 0, 0,
 106 #endif
 107         };
 108
 109         int needs_reset;
 110         unsigned bsp_apicid = 0, nodes;
 111         struct mem_controller ctrl[8];
 112
 113         if (!cpu_init_detectedx && boot_cpu()) {
 114                 /* Nothing special needs to be done to find bus 0 */
 115                 /* Allow the HT devices to be found */
 116                 enumerate_ht_chain();
 117         }
 118
 119         if (bist == 0)
 120                 bsp_apicid = init_cpus(cpu_init_detectedx);
 121
 122         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 123         uart_init();
 124         console_init();
 125
 126         /* Halt if there was a built in self test failure */
 127         report_bist_failure(bist);
 128
 129         setup_dl145g1_resource_map();
 130         //setup_default_resource_map();
 131
 132         needs_reset = setup_coherent_ht_domain();
 133
 134         wait_all_core0_started();
 135 #if CONFIG_LOGICAL_CPUS==1
 136         // It is said that we should start core1 after all core0 launched
 137         start_other_cores();
 138         wait_all_other_cores_started(bsp_apicid);
 139 #endif
 140
 141         needs_reset |= ht_setup_chains_x();
 142
 143         if (needs_reset) {
 144                 print_info("ht reset -\n");
 145                 soft_reset();
 146         }
 147
 148         enable_smbus();
 149
 150         int i;
 151         for(i=0;i<2;i++) {
 152                 activate_spd_rom(&ctrl[i]);
 153         }
 154         for(i=2;i<8;i<<=1) {
 155                 change_i2c_mux(i);
 156         }
 157
 158         //dump_spd_registers(&ctrl[0]);
 159         //dump_spd_registers(&ctrl[1]);
 160         //dump_smbus_registers();
 161
 162         allow_all_aps_stop(bsp_apicid);
 163
 164         nodes = get_nodes();
 165         //It's the time to set ctrl now;
 166         fill_mem_ctrl(nodes, ctrl, spd_addr);
 167
 168         memreset_setup();
 169         sdram_initialize(nodes, ctrl);
 170
 171         //dump_pci_devices();
 172
 173         post_cache_as_ram();
 174 }