1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <arch/ioapic.h>
4 #include <device/pci.h>
7 #include <cpu/amd/amdk8_sysconf.h>
9 extern unsigned char bus_isa;
10 extern unsigned char bus_8131_0;
11 extern unsigned char bus_8131_1;
12 extern unsigned char bus_8131_2;
13 extern unsigned char bus_8111_0;
14 extern unsigned char bus_8111_1;
15 extern unsigned apicid_8111;
16 extern unsigned apicid_8131_1;
17 extern unsigned apicid_8131_2;
19 extern unsigned sbdn3;
21 static void *smp_write_config_table(void *v)
23 struct mp_config_table *mc;
24 unsigned char bus_num;
26 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
28 mptable_init(mc, "DL145 G1 ", LAPIC_ADDR);
30 smp_write_processors(mc);
35 /* define bus and isa numbers */
36 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
37 smp_write_bus(mc, bus_num, "PCI ");
39 smp_write_bus(mc, bus_isa, "ISA ");
42 /*I/O APICs: APIC ID Version State Address*/
43 smp_write_ioapic(mc, apicid_8111, 0x20, IO_APIC_ADDR);
47 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
49 res = find_resource(dev, PCI_BASE_ADDRESS_0);
51 smp_write_ioapic(mc, apicid_8131_1, 0x20, res->base);
54 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
56 res = find_resource(dev, PCI_BASE_ADDRESS_0);
58 smp_write_ioapic(mc, apicid_8131_2, 0x20, res->base);
64 mptable_add_isa_interrupts(mc, bus_isa, apicid_8111, 0);
67 // The commented-out lines are auto-detected on my servers.
69 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
70 // Integrated SMBus 2.0
71 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|3, apicid_8111 , 0x15);
72 // Integrated AMD AC97 Audio
73 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11);
74 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12);
76 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x4 <<2)|0, apicid_8111 , 0x10);
77 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x0 <<2)|3, apicid_8111 , 0x13);
78 // On board ATI Rage XL
79 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14);
80 // On board Broadcom nics
81 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|0, apicid_8131_2, 0x03);
82 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x3 <<2)|1, apicid_8131_2, 0x00);
84 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02);
87 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|0, apicid_8131_1, 0x01);
88 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02);
89 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03);
90 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04);
92 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
93 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
94 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
95 /* There is no extension information... */
97 /* Compute the checksums */
98 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
99 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
100 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
101 mc, smp_next_mpe_entry(mc));
102 return smp_next_mpe_entry(mc);
105 unsigned long write_smp_table(unsigned long addr)
108 v = smp_write_floating_table(addr);
109 return (unsigned long)smp_write_config_table(v);