1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <arch/ioapic.h>
4 #include <device/pci.h>
7 #include <cpu/amd/amdk8_sysconf.h>
8 #include "mb_sysconf.h"
10 static void *smp_write_config_table(void *v)
12 struct mp_config_table *mc;
15 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
17 mptable_init(mc, LOCAL_APIC_ADDR);
19 smp_write_processors(mc);
23 struct mb_sysconf_t *m = sysconf.mb;
25 mptable_write_buses(mc, NULL, &bus_isa);
27 /*I/O APICs: APIC ID Version State Address*/
28 smp_write_ioapic(mc, m->apicid_8111, 0x20, IO_APIC_ADDR);
32 dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3,1));
34 res = find_resource(dev, PCI_BASE_ADDRESS_0);
36 smp_write_ioapic(mc, m->apicid_8131_1, 0x20, res->base);
39 dev = dev_find_slot(m->bus_8131_0, PCI_DEVFN(m->sbdn3+1,1));
41 res = find_resource(dev, PCI_BASE_ADDRESS_0);
43 smp_write_ioapic(mc, m->apicid_8131_2, 0x20, res->base);
49 mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0);
52 // The commented-out lines are auto-detected on my servers.
54 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
55 // Integrated SMBus 2.0
56 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|3, apicid_8111 , 0x15);
57 // Integrated AMD AC97 Audio
58 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11);
59 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12);
61 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x4 <<2)|0, m->apicid_8111 , 0x10);
62 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x0 <<2)|3, m->apicid_8111 , 0x13);
63 // On board ATI Rage XL
64 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14);
65 // On board Broadcom nics
66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|0, m->apicid_8131_2, 0x03);
67 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|1, m->apicid_8131_2, 0x00);
69 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02);
72 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|0, m->apicid_8131_1, 0x01);
73 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02);
74 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03);
75 //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04);
77 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
78 mptable_lintsrc(mc, bus_isa);
79 /* There is no extension information... */
81 /* Compute the checksums */
82 return mptable_finalize(mc);
85 unsigned long write_smp_table(unsigned long addr)
88 v = smp_write_floating_table(addr, 0);
89 return (unsigned long)smp_write_config_table(v);