2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Wang Qing Pei <wangqingpei@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 //#define SYSTEM_TYPE 0 /* SERVER */
21 #define SYSTEM_TYPE 1 /* DESKTOP */
22 //#define SYSTEM_TYPE 2 /* MOBILE */
26 #include <device/pci_def.h>
27 #include <device/pci_ids.h>
29 #include <device/pnp_def.h>
30 #include <arch/romcc_io.h>
31 #include <cpu/x86/lapic.h>
32 #include <console/console.h>
33 #include <cpu/amd/model_10xxx_rev.h>
34 #include "northbridge/amd/amdfam10/raminit.h"
35 #include "northbridge/amd/amdfam10/amdfam10.h"
37 #include "cpu/x86/lapic/boot_cpu.c"
38 #include "northbridge/amd/amdfam10/reset_test.c"
39 #include <console/loglevel.h>
40 #include "cpu/x86/bist.h"
41 #include "superio/ite/it8718f/early_serial.c"
42 #include "cpu/x86/mtrr/earlymtrr.c"
43 #include <cpu/amd/mtrr.h>
44 #include "northbridge/amd/amdfam10/setup_resource_map.c"
45 #include "southbridge/amd/rs780/early_setup.c"
46 #include "southbridge/amd/sb700/sb700.h"
47 #include "southbridge/amd/sb700/smbus.h"
48 #include "northbridge/amd/amdfam10/debug.c"
50 static void activate_spd_rom(const struct mem_controller *ctrl) { }
52 static int spd_read_byte(u32 device, u32 address)
54 return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
57 #include "northbridge/amd/amdfam10/amdfam10.h"
58 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
59 #include "northbridge/amd/amdfam10/pci.c"
60 #include "resourcemap.c"
61 #include "cpu/amd/quadcore/quadcore.c"
62 #include "cpu/amd/car/post_cache_as_ram.c"
63 #include "cpu/amd/microcode/microcode.c"
65 #if CONFIG_UPDATE_CPU_MICROCODE
66 #include "cpu/amd/model_10xxx/update_microcode.c"
69 #include "cpu/amd/model_10xxx/init_cpus.c"
70 #include "northbridge/amd/amdfam10/early_ht.c"
73 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
75 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
76 static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
77 u32 bsp_apicid = 0, val;
80 if (!cpu_init_detectedx && boot_cpu()) {
81 /* Nothing special needs to be done to find bus 0 */
82 /* Allow the HT devices to be found */
83 /* mov bsp to bus 0xff when > 8 nodes */
84 set_bsp_node_CHtExtNodeCfgEn();
86 sb7xx_51xx_pci_port80();
92 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
93 /* All cores run this but the BSP(node0,core0) is the only core that returns. */
99 sb7xx_51xx_lpc_init();
101 it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
102 it8718f_disable_reboot();
105 // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
107 /* Halt if there was a built in self test failure */
108 report_bist_failure(bist);
112 printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
113 printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
114 printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid);
115 printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
117 /* Setup sysinfo defaults */
118 set_sysinfo_in_ram(0);
120 #if CONFIG_UPDATE_CPU_MICROCODE
121 update_microcode(val);
128 amd_ht_init(sysinfo);
131 /* Setup nodes PCI space and start core 0 AP init. */
132 finalize_node_setup(sysinfo);
134 /* Setup any mainboard PCI settings etc. */
135 setup_mb_resource_map();
138 /* wait for all the APs core0 started by finalize_node_setup. */
139 /* FIXME: A bunch of cores are going to start output to serial at once.
140 It would be nice to fixup prink spinlocks for ROM XIP mode.
141 I think it could be done by putting the spinlock flag in the cache
142 of the BSP located right after sysinfo.
144 wait_all_core0_started();
146 #if CONFIG_LOGICAL_CPUS==1
147 /* Core0 on each node is configured. Now setup any additional cores. */
148 printk(BIOS_DEBUG, "start_other_cores()\n");
151 wait_all_other_cores_started(bsp_apicid);
156 /* run _early_setup before soft-reset. */
158 sb7xx_51xx_early_setup();
160 #if CONFIG_SET_FIDVID
161 msr = rdmsr(0xc0010071);
162 printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
164 /* FIXME: The sb fid change may survive the warm reset and only
165 need to be done once.*/
166 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
170 if (!warm_reset_detect(0)) { // BSP is node 0
171 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
173 init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
178 /* show final fid and vid */
179 msr=rdmsr(0xc0010071);
180 printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
185 /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
186 if (!warm_reset_detect(0)) {
187 print_info("...WARM RESET...\n\n\n");
189 die("After soft_reset_x - shouldn't see this message!!!\n");
194 /* It's the time to set ctrl in sysinfo now; */
195 printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
196 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
200 // die("Die Before MCT init.");
202 printk(BIOS_DEBUG, "raminit_amdmct()\n");
203 raminit_amdmct(sysinfo);
207 dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
208 dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
209 dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
210 dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
213 // die("After MCT init before CAR disabled.");
215 rs780_before_pci_init();
216 sb7xx_51xx_before_pci_init();
219 printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
220 post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
221 post_code(0x43); // Should never see this post code.
225 * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
227 * This routine is called every time a non-coherent chain is processed.
228 * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
229 * swap list. The first part of the list controls the BUID assignment and the
230 * second part of the list provides the device to device linking. Device orientation
231 * can be detected automatically, or explicitly. See documentation for more details.
233 * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
234 * based on each device's unit count.
237 * @param[in] u8 node = The node on which this chain is located
238 * @param[in] u8 link = The link on the host for this chain
239 * @param[out] u8** list = supply a pointer to a list
240 * @param[out] BOOL result = true to use a manual list
241 * false to initialize the link automatically
243 BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
245 static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
246 /* If the BUID was adjusted in early_ht we need to do the manual override */
247 if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
248 printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
249 if ((node == 0) && (link == 0)) { /* BSP SB link */