src/mainboard/gigabyte/m57sli/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20  */
  21
  22 #if CONFIG_K8_REV_F_SUPPORT == 1
  23 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  24 #endif
  25
  26 #include <stdint.h>
  27 #include <string.h>
  28 #include <device/pci_def.h>
  29 #include <device/pci_ids.h>
  30 #include <arch/io.h>
  31 #include <device/pnp_def.h>
  32 #include <arch/romcc_io.h>
  33 #include <cpu/x86/lapic.h>
  34 #include <pc80/mc146818rtc.h>
  35
  36 #include <console/console.h>
  37 #include <usbdebug.h>
  38 #include <spd.h>
  39
  40 #include <cpu/amd/model_fxx_rev.h>
  41
  42 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
  43 #include "northbridge/amd/amdk8/raminit.h"
  44 #include "cpu/amd/model_fxx/apic_timer.c"
  45 #include "lib/delay.c"
  46
  47 #include "cpu/x86/lapic/boot_cpu.c"
  48 #include "northbridge/amd/amdk8/reset_test.c"
  49 #include "superio/ite/it8716f/it8716f_early_serial.c"
  50 #include "superio/ite/it8716f/it8716f_early_init.c"
  51
  52 #include "cpu/x86/bist.h"
  53
  54 #include "northbridge/amd/amdk8/debug.c"
  55
  56 #include "cpu/x86/mtrr/earlymtrr.c"
  57
  58 #include "northbridge/amd/amdk8/setup_resource_map.c"
  59
  60 #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
  61 #define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO)
  62
  63 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
  64
  65 static void memreset(int controllers, const struct mem_controller *ctrl)
  66 {
  67 }
  68
  69 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  70 {
  71         /* nothing to do */
  72 }
  73
  74 static inline int spd_read_byte(unsigned device, unsigned address)
  75 {
  76         return smbus_read_byte(device, address);
  77 }
  78
  79 #define MCP55_MB_SETUP \
  80         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x68,/* GPIO38 PCI_REQ3 */ \
  81         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \
  82         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x68,/* GPIO40 PCI_GNT2 */ \
  83         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x68,/* GPIO41 PCI_REQ2 */ \
  84         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
  85         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
  86
  87 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
  88 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
  89
  90
  91
  92 #include "northbridge/amd/amdk8/amdk8_f.h"
  93 #include "northbridge/amd/amdk8/incoherent_ht.c"
  94 #include "northbridge/amd/amdk8/coherent_ht.c"
  95 #include "northbridge/amd/amdk8/raminit_f.c"
  96 #include "lib/generic_sdram.c"
  97
  98 #include "resourcemap.c"
  99
 100 #include "cpu/amd/dualcore/dualcore.c"
 101
 102 #include "cpu/amd/car/post_cache_as_ram.c"
 103
 104 #include "cpu/amd/model_fxx/init_cpus.c"
 105
 106 #include "cpu/amd/model_fxx/fidvid.c"
 107
 108 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 109 #include "northbridge/amd/amdk8/early_ht.c"
 110
 111 static void sio_setup(void)
 112 {
 113         uint32_t dword;
 114         uint8_t byte;
 115
 116         byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
 117         byte |= 0x20;
 118         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 119
 120         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
 121         dword |= (1<<0);
 122         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 123
 124         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
 125         dword |= (1<<16);
 126         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
 127 }
 128
 129 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 130 {
 131         static const uint16_t spd_addr [] = {
 132                         // Node 0
 133                         DIMM0, DIMM2, 0, 0,
 134                         DIMM1, DIMM3, 0, 0,
 135                         // Node 1
 136                         DIMM4, DIMM6, 0, 0,
 137                         DIMM5, DIMM7, 0, 0,
 138         };
 139
 140         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 141                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 142
 143         int needs_reset = 0;
 144         unsigned bsp_apicid = 0;
 145         uint8_t tmp = 0;
 146
 147         if (!cpu_init_detectedx && boot_cpu()) {
 148                 /* Nothing special needs to be done to find bus 0 */
 149                 /* Allow the HT devices to be found */
 150
 151                 enumerate_ht_chain();
 152
 153                 sio_setup();
 154
 155                 /* Setup the mcp55 */
 156                 mcp55_enable_rom();
 157         }
 158
 159         if (bist == 0) {
 160                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 161         }
 162
 163         pnp_enter_ext_func_mode(SERIAL_DEV);
 164         /* The following line will set CLKIN to 24 MHz, external */
 165         pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11);
 166         tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP);
 167         /* Is serial flash enabled? Then enable writing to serial flash. */
 168         if (tmp & 0x0e) {
 169                 pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP, tmp | 0x10);
 170                 pnp_set_logical_device(GPIO_DEV);
 171                 /* Set Serial Flash interface to 0x0820 */
 172                 pnp_write_config(GPIO_DEV, 0x64, 0x08);
 173                 pnp_write_config(GPIO_DEV, 0x65, 0x20);
 174                 /* We can get away with not resetting the logical device because
 175                  * it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE) will do that.
 176                  */
 177         }
 178         it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
 179         pnp_exit_ext_func_mode(SERIAL_DEV);
 180
 181         setup_mb_resource_map();
 182
 183         uart_init();
 184
 185         /* Halt if there was a built in self test failure */
 186         report_bist_failure(bist);
 187
 188 #if CONFIG_USBDEBUG
 189         mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
 190         early_usbdebug_init();
 191 #endif
 192         console_init();
 193         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 194
 195         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 196
 197 #if CONFIG_MEM_TRAIN_SEQ == 1
 198         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 199 #endif
 200         setup_coherent_ht_domain(); // routing table and start other core0
 201
 202         wait_all_core0_started();
 203 #if CONFIG_LOGICAL_CPUS==1
 204         // It is said that we should start core1 after all core0 launched
 205         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 206          * So here need to make sure last core0 is started, esp for two way system,
 207          * (there may be apic id conflicts in that case)
 208          */
 209         start_other_cores();
 210         wait_all_other_cores_started(bsp_apicid);
 211 #endif
 212
 213         /* it will set up chains and store link pair for optimization later */
 214         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 215
 216 #if CONFIG_SET_FIDVID
 217
 218         {
 219                 msr_t msr;
 220                 msr=rdmsr(0xc0010042);
 221                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 222
 223         }
 224
 225         enable_fid_change();
 226
 227         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 228
 229         init_fidvid_bsp(bsp_apicid);
 230
 231         // show final fid and vid
 232         {
 233                 msr_t msr;
 234                 msr=rdmsr(0xc0010042);
 235                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 236
 237         }
 238 #endif
 239
 240         init_timer(); // Need to use TMICT to synconize FID/VID
 241
 242         needs_reset |= optimize_link_coherent_ht();
 243         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 244         needs_reset |= mcp55_early_setup_x();
 245
 246         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 247         if (needs_reset) {
 248                 print_info("ht reset -\n");
 249                 soft_reset();
 250         }
 251         allow_all_aps_stop(bsp_apicid);
 252
 253         //It's the time to set ctrl in sysinfo now;
 254         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 255
 256         enable_smbus();
 257
 258         /* all ap stopped? */
 259
 260         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 261
 262         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 263
 264 }
 265