2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
6 * Copyright (C) 2009 Harald Gutmann <harald.gutmann@gmx.net>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 #include <console/console.h>
24 #include <arch/smp/mpspec.h>
25 #include <device/pci.h>
28 #include <cpu/amd/amdk8_sysconf.h>
30 extern unsigned char bus_isa;
31 extern unsigned char bus_mcp55[8]; //1
33 extern unsigned apicid_mcp55;
35 extern unsigned bus_type[256];
37 static void *smp_write_config_table(void *v)
39 struct mp_config_table *mc;
43 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
45 mptable_init(mc, "GA-M57SLI-S4", LAPIC_ADDR);
47 smp_write_processors(mc);
53 /* define bus and isa numbers */
54 for(j= 0; j < 256 ; j++) {
56 smp_write_bus(mc, j, "PCI ");
58 smp_write_bus(mc, bus_isa, "ISA ");
60 /*I/O APICs: APIC ID Version State Address*/
65 dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
67 res = find_resource(dev, PCI_BASE_ADDRESS_1);
69 smp_write_ioapic(mc, apicid_mcp55, 0x11, res->base);
71 /* set up the interrupt registers of mcp55 */
72 pci_write_config32(dev, 0x7c, 0xc643c643);
73 pci_write_config32(dev, 0x80, 0x8da01009);
74 pci_write_config32(dev, 0x84, 0x200018d2);
78 mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0);
80 /* PCI interrupts are level triggered, and are
81 * associated with a specific bus/device/function tuple.
83 #define PCI_INT(bus, dev, fn, pin) \
84 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,\
85 bus_mcp55[bus], (((dev)<<2)|(fn)), apicid_mcp55, (pin))
87 PCI_INT(0,sbdn+1,1, 10); /* SMBus */
88 PCI_INT(0,sbdn+2,0, 22); /* USB */
89 PCI_INT(0,sbdn+2,1, 23); /* USB */
90 PCI_INT(0,sbdn+4,0, 21); /* IDE */
91 PCI_INT(0,sbdn+5,0, 20); /* SATA */
92 PCI_INT(0,sbdn+5,1, 21); /* SATA */
93 PCI_INT(0,sbdn+5,2, 22); /* SATA */
94 PCI_INT(0,sbdn+6,1, 23); /* HD Audio */
95 PCI_INT(0,sbdn+8,0, 20); /* GBit Ethernet */
97 /* The PCIe slots, each on its own bus */
102 PCI_INT(j,0,i, 16+k);
108 /* On bus 1: the PCI bus slots...
109 pyhsical PCI slots are j = 7,8
116 PCI_INT(1,j,i, 16+k);
121 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
122 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
123 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
124 /* There is no extension information... */
126 /* Compute the checksums */
127 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
128 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
129 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
130 mc, smp_next_mpe_entry(mc));
131 return smp_next_mpe_entry(mc);
134 unsigned long write_smp_table(unsigned long addr)
137 v = smp_write_floating_table(addr);
138 return (unsigned long)smp_write_config_table(v);