src/mainboard/gigabyte/m57sli/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright (C) 2007 AMD
   5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6 ##
   7 ## This program is free software; you can redistribute it and/or modify
   8 ## it under the terms of the GNU General Public License as published by
   9 ## the Free Software Foundation; either version 2 of the License, or
  10 ## (at your option) any later version.
  11 ##
  12 ## This program is distributed in the hope that it will be useful,
  13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ## GNU General Public License for more details.
  16 ##
  17 ## You should have received a copy of the GNU General Public License
  18 ## along with this program; if not, write to the Free Software
  19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20 ##
  21
  22 ## XIP_ROM_SIZE must be a power of 2.
  23 default XIP_ROM_SIZE = 64 * 1024
  24 include /config/failovercalculation.lb
  25
  26 arch i386 end
  27
  28 ##
  29 ## Build the objects we have code for in this directory.
  30 ##
  31
  32 driver mainboard.o
  33 #needed by irq_tables and mptable and acpi_tables
  34 object get_bus_conf.o
  35
  36 if HAVE_MP_TABLE object mptable.o end
  37 if HAVE_PIRQ_TABLE object irq_tables.o end
  38 #object reset.o
  39
  40         if CONFIG_USE_INIT
  41                 makerule ./cache_as_ram_auto.o
  42                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  43                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
  44                 end
  45         else
  46                 makerule ./cache_as_ram_auto.inc
  47                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  48                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
  49                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  50                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  51                 end
  52         end
  53
  54 if USE_FAILOVER_IMAGE
  55 else
  56     if CONFIG_AP_CODE_IN_CAR
  57         makerule ./apc_auto.o
  58                 depends "$(MAINBOARD)/apc_auto.c option_table.h"
  59                 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@"
  60         end
  61         ldscript /arch/i386/init/ldscript_apc.lb
  62     end
  63 end
  64
  65
  66 ##
  67 ## Build our 16 bit and 32 bit coreboot entry code
  68 ##
  69 if HAVE_FAILOVER_BOOT
  70     if USE_FAILOVER_IMAGE
  71         mainboardinit cpu/x86/16bit/entry16.inc
  72         ldscript /cpu/x86/16bit/entry16.lds
  73     end
  74 else
  75     if USE_FALLBACK_IMAGE
  76         mainboardinit cpu/x86/16bit/entry16.inc
  77         ldscript /cpu/x86/16bit/entry16.lds
  78     end
  79 end
  80
  81 mainboardinit cpu/x86/32bit/entry32.inc
  82
  83         if CONFIG_USE_INIT
  84                 ldscript /cpu/x86/32bit/entry32.lds
  85         end
  86
  87         if CONFIG_USE_INIT
  88                 ldscript /cpu/amd/car/cache_as_ram.lds
  89         end
  90
  91 ##
  92 ## Build our reset vector (This is where coreboot is entered)
  93 ##
  94 if HAVE_FAILOVER_BOOT
  95     if USE_FAILOVER_IMAGE
  96         mainboardinit cpu/x86/16bit/reset16.inc
  97         ldscript /cpu/x86/16bit/reset16.lds
  98     else
  99         mainboardinit cpu/x86/32bit/reset32.inc
 100         ldscript /cpu/x86/32bit/reset32.lds
 101     end
 102 else
 103     if USE_FALLBACK_IMAGE
 104         mainboardinit cpu/x86/16bit/reset16.inc
 105         ldscript /cpu/x86/16bit/reset16.lds
 106     else
 107         mainboardinit cpu/x86/32bit/reset32.inc
 108         ldscript /cpu/x86/32bit/reset32.lds
 109     end
 110 end
 111
 112 ##
 113 ## Include an id string (For safe flashing)
 114 ##
 115 mainboardinit southbridge/nvidia/mcp55/id.inc
 116 ldscript /southbridge/nvidia/mcp55/id.lds
 117
 118 ##
 119 ## ROMSTRAP table for MCP55
 120 ##
 121 if HAVE_FAILOVER_BOOT
 122     if USE_FAILOVER_IMAGE
 123         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 124         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 125     end
 126 else
 127     if USE_FALLBACK_IMAGE
 128         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 129         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 130     end
 131 end
 132
 133         ##
 134         ## Setup Cache-As-Ram
 135         ##
 136         mainboardinit cpu/amd/car/cache_as_ram.inc
 137
 138 ###
 139 ### This is the early phase of coreboot startup
 140 ### Things are delicate and we test to see if we should
 141 ### failover to another image.
 142 ###
 143 if HAVE_FAILOVER_BOOT
 144     if USE_FAILOVER_IMAGE
 145                 ldscript /arch/i386/lib/failover_failover.lds
 146     end
 147 else
 148     if USE_FALLBACK_IMAGE
 149                 ldscript /arch/i386/lib/failover.lds
 150     end
 151 end
 152
 153 if HAVE_FANCTL
 154         object fanctl.o
 155 end
 156
 157 ##
 158 ## Setup RAM
 159 ##
 160         if CONFIG_USE_INIT
 161                 initobject cache_as_ram_auto.o
 162         else
 163                 mainboardinit ./cache_as_ram_auto.inc
 164         end
 165
 166 ##
 167 ## ACPI Support
 168 ##
 169 if HAVE_ACPI_TABLES
 170         object acpi_tables.o
 171         makerule dsdt.c
 172                 depends "$(MAINBOARD)/dsdt.asl"
 173                 action  "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.asl"
 174                 action  "mv dsdt.hex dsdt.c"
 175         end
 176         object ./dsdt.o
 177 end
 178
 179 ##
 180 ## Include the secondary Configuration files
 181 ##
 182 config chip.h
 183
 184 chip northbridge/amd/amdk8/root_complex
 185         device apic_cluster 0 on
 186                 chip cpu/amd/socket_AM2
 187                         device apic 0 on end
 188                 end
 189         end
 190         device pci_domain 0 on
 191                 chip northbridge/amd/amdk8 #mc0
 192                         device pci 18.0 on
 193                                 #  devices on link 0, link 0 == LDT 0
 194                                 chip southbridge/nvidia/mcp55
 195                                         device pci 0.0 on end   # HT
 196                                         device pci 1.0 on # LPC
 197                                                 chip superio/ite/it8716f
 198                                                         # Floppy and any LDN
 199                                                         device pnp 2e.0 off
 200                                                         # Watchdog from CLKIN, CLKIN = 24 MHz
 201                                                                 irq 0x23 = 0x11
 202                                                         # Serial Flash (SPI only)
 203                                                                 #0x24 = 0x1a
 204                                                                 io 0x60 = 0x3f0
 205                                                                 irq 0x70 = 6
 206                                                                 drq 0x74 = 2
 207                                                         end
 208                                                         device pnp 2e.1 on #  Com1
 209                                                                 io 0x60 = 0x3f8
 210                                                                 irq 0x70 = 4
 211                                                         end
 212                                                         device pnp 2e.2 off #  Com2
 213                                                                 io 0x60 = 0x2f8
 214                                                                 irq 0x70 = 3
 215                                                         end
 216                                                         device pnp 2e.3 off #  Parallel Port
 217                                                                 io 0x60 = 0x378
 218                                                                 irq 0x70 = 7
 219                                                         end
 220                                                         device pnp 2e.4 on #  EC
 221                                                                 io 0x60 = 0x290
 222                                                                 io 0x62 = 0x230
 223                                                                 irq 0x70 = 9
 224                                                         end
 225                                                         device pnp 2e.5 on #  Keyboard
 226                                                                 io 0x60 = 0x60
 227                                                                 io 0x62 = 0x64
 228                                                                 irq 0x70 = 1
 229                                                         end
 230                                                         device pnp 2e.6 on #  Mouse
 231                                                                 irq 0x70 = 12
 232                                                         end
 233                                                         device pnp 2e.7 on #  GPIO, SPI flash
 234                                                                 # pin 84 is not GP10
 235                                                                 irq 0x25 = 0x0
 236                                 # pin 21 is GP26, pin 26 is GP21, pin 27 is GP20
 237                                                                 irq 0x26 = 0x43
 238                                                                 # pin 13 is GP35
 239                                                                 irq 0x27 = 0x20
 240                                                                 # pin 70 is not GP46
 241                                                                 #irq 0x28 = 0x0
 242                                 # pin 6,3,128,127,126 is GP63,64,65,66,67
 243                                                                 irq 0x29 = 0x81
 244                                 # Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V
 245                                                                 #irq 0x2c = 0x1f
 246                                 # Simple I/O base
 247                                                                 io 0x62 = 0x800
 248                                 # Serial Flash I/O (SPI only)
 249                                                                 io 0x64 = 0x820
 250                                 # watch dog force timeout (parallel flash only)
 251                                                                 #irq 0x71 = 0x1
 252                                                                 # No WDT interrupt
 253                                                                 irq 0x72 = 0x0
 254                                         # GPIO pin set 1 disable internal pullup
 255                                                                 irq 0xb8 = 0x0
 256                                         # GPIO pin set 5 enable internal pullup
 257                                                                 irq 0xbc = 0x01
 258                                         # SIO pin set 1 alternate function
 259                                                                 #irq 0xc0 = 0x0
 260                                         # SIO pin set 2 mixed function
 261                                                                 irq 0xc1 = 0x43
 262                                         # SIO pin set 3 mixed function
 263                                                                 irq 0xc2 = 0x20
 264                                         # SIO pin set 4 alternate function
 265                                                                 #irq 0xc3 = 0x0
 266                                         # SIO pin set 1 input mode
 267                                                                 #irq 0xc8 = 0x0
 268                                         # SIO pin set 2 input mode
 269                                                                 irq 0xc9 = 0x0
 270                                         # SIO pin set 4 input mode
 271                                                                 #irq 0xcb = 0x0
 272                                         # Generate SMI# on EC IRQ
 273                                                                 #irq 0xf0 = 0x10
 274                                         # SMI# level trigger
 275                                                                 #irq 0xf1 = 0x40
 276                                         # HWMON alert beep pin location
 277                                                                 irq 0xf6 = 0x28
 278                                                         end
 279                                                         device pnp 2e.8 off #  MIDI
 280                                                                 io 0x60 = 0x300
 281                                                                 irq 0x70 = 10
 282                                                         end
 283                                                         device pnp 2e.9 off #  GAME
 284                                                                 io 0x60 = 0x220
 285                                                         end
 286                                                         device pnp 2e.a off end #  CIR
 287                                                 end
 288                                         end
 289                                         device pci 1.1 on # SM 0
 290                                                 chip drivers/generic/generic #dimm 0-0-0
 291                                                         device i2c 50 on end
 292                                                 end
 293                                                 chip drivers/generic/generic #dimm 0-0-1
 294                                                         device i2c 51 on end
 295                                                 end
 296                                                 chip drivers/generic/generic #dimm 0-1-0
 297                                                         device i2c 52 on end
 298                                                 end
 299                                                 chip drivers/generic/generic #dimm 0-1-1
 300                                                         device i2c 53 on end
 301                                                 end
 302                                                 chip drivers/generic/generic #dimm 1-0-0
 303                                                         device i2c 54 on end
 304                                                 end
 305                                                 chip drivers/generic/generic #dimm 1-0-1
 306                                                         device i2c 55 on end
 307                                                 end
 308                                                 chip drivers/generic/generic #dimm 1-1-0
 309                                                         device i2c 56 on end
 310                                                 end
 311                                                 chip drivers/generic/generic #dimm 1-1-1
 312                                                         device i2c 57 on end
 313                                                 end
 314                                         end # SM
 315 #WTF?!? We already have device pci 1.1 in the section above
 316                                         device pci 1.1 on # SM 1
 317 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
 318 #                                                chip drivers/generic/generic #PCIXA Slot1
 319 #                                                        device i2c 50 on end
 320 #                                                end
 321 #                                                chip drivers/generic/generic #PCIXB Slot1
 322 #                                                        device i2c 51 on end
 323 #                                                end
 324 #                                                chip drivers/generic/generic #PCIXB Slot2
 325 #                                                        device i2c 52 on end
 326 #                                                end
 327 #                                                chip drivers/generic/generic #PCI Slot1
 328 #                                                        device i2c 53 on end
 329 #                                                end
 330 #                                                chip drivers/generic/generic #Master MCP55 PCI-E
 331 #                                                        device i2c 54 on end
 332 #                                                end
 333 #                                                chip drivers/generic/generic #Slave MCP55 PCI-E
 334 #                                                        device i2c 55 on end
 335 #                                                end
 336                                                 chip drivers/generic/generic #MAC EEPROM
 337                                                         device i2c 51 on end
 338                                                 end
 339
 340                                         end # SM
 341                                         device pci 2.0 on end # USB 1.1
 342                                         device pci 2.1 on end # USB 2
 343                                         device pci 4.0 on end # IDE
 344                                         device pci 5.0 on end # SATA 0
 345                                         device pci 5.1 on end # SATA 1
 346                                         device pci 5.2 on end # SATA 2
 347                                         device pci 6.0 on end # PCI
 348                                         device pci 6.1 on end # AZA
 349                                         device pci 8.0 on end # NIC
 350                                         device pci 9.0 off end # NIC
 351                                         device pci a.0 on end # PCI E 5
 352                                         device pci b.0 on end # PCI E 4
 353                                         device pci c.0 on end # PCI E 3
 354                                         device pci d.0 on end # PCI E 2
 355                                         device pci e.0 on end # PCI E 1
 356                                         device pci f.0 on end # PCI E 0
 357                                         register "ide0_enable" = "1"
 358                                         register "sata0_enable" = "1"
 359                                         register "sata1_enable" = "1"
 360                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 361                                         register "mac_eeprom_addr" = "0x51"
 362                                 end
 363                         end #  device pci 18.0
 364                         device pci 18.0 on end # Link 1
 365                         device pci 18.0 on end
 366                         device pci 18.1 on end
 367                         device pci 18.2 on end
 368                         device pci 18.3 on end
 369                 end # mc0
 370
 371         end # PCI domain
 372
 373 #       chip drivers/generic/debug
 374 #               device pnp 0.0 off end # chip name
 375 #                device pnp 0.1 on end # pci_regs_all
 376 #                device pnp 0.2 on end # mem
 377 #                device pnp 0.3 off end # cpuid
 378 #                device pnp 0.4 on end # smbus_regs_all
 379 #                device pnp 0.5 off end # dual core msr
 380 #                device pnp 0.6 off end # cache size
 381 #               device pnp 0.7 off end # tsc
 382 #                device pnp 0.8 off  end # io
 383 #                device pnp 0.9 off end # io
 384 #       end
 385 end #root_complex