2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
6 * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
7 * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <console/console.h>
25 #include <arch/smp/mpspec.h>
26 #include <device/pci.h>
30 #include <cpu/amd/amdk8_sysconf.h>
31 extern unsigned char bus_isa;
32 extern unsigned char bus_sis966[8]; //1
34 extern unsigned apicid_sis966;
36 extern unsigned bus_type[256];
38 static void *smp_write_config_table(void *v)
40 static const char sig[4] = "PCMP";
41 static const char oem[8] = "COREBOOT";
42 static const char productid[12] = "GA-2761GXDK ";
43 struct mp_config_table *mc;
48 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
49 memset(mc, 0, sizeof(*mc));
51 memcpy(mc->mpc_signature, sig, sizeof(sig));
52 mc->mpc_length = sizeof(*mc); /* initially just the header */
54 mc->mpc_checksum = 0; /* not yet computed */
55 memcpy(mc->mpc_oem, oem, sizeof(oem));
56 memcpy(mc->mpc_productid, productid, sizeof(productid));
59 mc->mpc_entry_count = 0; /* No entries yet... */
60 mc->mpc_lapic = LAPIC_ADDR;
65 smp_write_processors(mc);
71 /* define bus and isa numbers */
72 for(j= 0; j < 256 ; j++) {
74 smp_write_bus(mc, j, "PCI ");
76 smp_write_bus(mc, bus_isa, "ISA ");
78 /*I/O APICs: APIC ID Version State Address*/
84 dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn+ 0x1,0));
86 res = find_resource(dev, PCI_BASE_ADDRESS_1);
88 smp_write_ioapic(mc, apicid_sis966, 0x11, res->base);
92 pci_write_config32(dev, 0x7c, dword);
95 pci_write_config32(dev, 0x80, dword);
98 pci_write_config32(dev, 0x84, dword);
103 mptable_add_isa_interrupts(mc, bus_isa, apicid_sis966, 0);
105 /* PCI interrupts are level triggered, and are
106 * associated with a specific bus/device/function tuple.
108 #define PCI_INT(bus, dev, fn, pin) \
109 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[bus], (((dev)<<2)|(fn)), apicid_sis966, (pin))
111 PCI_INT(0, sbdn+1, 1, 0xa);
112 PCI_INT(0, sbdn+2, 0, 0x16); // 22
113 PCI_INT(0, sbdn+2, 1, 0x17); // 23
114 PCI_INT(0, sbdn+6, 1, 0x17); // 23
115 PCI_INT(0, sbdn+5, 0, 0x14); // 20
116 PCI_INT(0, sbdn+5, 1, 0x17); // 23
117 PCI_INT(0, sbdn+5, 2, 0x15); // 21
118 PCI_INT(0, sbdn+8, 0, 0x16); // 22
120 for(j=7; j>=2; j--) {
121 if(!bus_sis966[j]) continue;
123 PCI_INT(j, 0x00, i, 0x10 + (2+j+i+4-sbdn%4)%4);
129 PCI_INT(1, 0x06+j, i, 0x10 + (2+i+j)%4);
132 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
133 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
134 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
135 /* There is no extension information... */
137 /* Compute the checksums */
138 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
139 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
140 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
141 mc, smp_next_mpe_entry(mc));
142 return smp_next_mpe_entry(mc);
145 unsigned long write_smp_table(unsigned long addr)
148 v = smp_write_floating_table(addr);
149 return (unsigned long)smp_write_config_table(v);