2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
6 * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
7 * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <console/console.h>
25 #include <arch/smp/mpspec.h>
26 #include <device/pci.h>
29 #include <cpu/amd/amdk8_sysconf.h>
31 extern unsigned char bus_sis966[8]; //1
33 extern unsigned apicid_sis966;
35 static void *smp_write_config_table(void *v)
37 struct mp_config_table *mc;
41 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
43 mptable_init(mc, LAPIC_ADDR);
45 smp_write_processors(mc);
50 mptable_write_buses(mc, NULL, &bus_isa);
52 /*I/O APICs: APIC ID Version State Address*/
58 dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn+ 0x1,0));
60 res = find_resource(dev, PCI_BASE_ADDRESS_1);
62 smp_write_ioapic(mc, apicid_sis966, 0x11, res->base);
66 pci_write_config32(dev, 0x7c, dword);
69 pci_write_config32(dev, 0x80, dword);
72 pci_write_config32(dev, 0x84, dword);
77 mptable_add_isa_interrupts(mc, bus_isa, apicid_sis966, 0);
79 /* PCI interrupts are level triggered, and are
80 * associated with a specific bus/device/function tuple.
82 #define PCI_INT(bus, dev, fn, pin) \
83 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[bus], (((dev)<<2)|(fn)), apicid_sis966, (pin))
85 PCI_INT(0, sbdn+1, 1, 0xa);
86 PCI_INT(0, sbdn+2, 0, 0x16); // 22
87 PCI_INT(0, sbdn+2, 1, 0x17); // 23
88 PCI_INT(0, sbdn+6, 1, 0x17); // 23
89 PCI_INT(0, sbdn+5, 0, 0x14); // 20
90 PCI_INT(0, sbdn+5, 1, 0x17); // 23
91 PCI_INT(0, sbdn+5, 2, 0x15); // 21
92 PCI_INT(0, sbdn+8, 0, 0x16); // 22
95 if(!bus_sis966[j]) continue;
97 PCI_INT(j, 0x00, i, 0x10 + (2+j+i+4-sbdn%4)%4);
103 PCI_INT(1, 0x06+j, i, 0x10 + (2+i+j)%4);
106 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
107 mptable_lintsrc(mc, bus_isa);
108 /* There is no extension information... */
110 /* Compute the checksums */
111 return mptable_finalize(mc);
114 unsigned long write_smp_table(unsigned long addr)
117 v = smp_write_floating_table(addr, 0);
118 return (unsigned long)smp_write_config_table(v);