src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
   7  * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  22  */
  23
  24 /* This file was generated by getpir.c, do not modify!
  25    (but if you do, please run checkpir on it to verify)
  26    Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
  27
  28    Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
  29 */
  30 #include <console/console.h>
  31 #include <device/pci.h>
  32 #include <string.h>
  33 #include <stdint.h>
  34 #include <arch/pirq_routing.h>
  35 #include <device/pci_ids.h>
  36 #include <cpu/amd/amdk8_sysconf.h>
  37
  38 static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
  39                 uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
  40                 uint8_t slot, uint8_t rfu)
  41 {
  42         pirq_info->bus = bus;
  43         pirq_info->devfn = devfn;
  44                 pirq_info->irq[0].link = link0;
  45                 pirq_info->irq[0].bitmap = bitmap0;
  46                 pirq_info->irq[1].link = link1;
  47                 pirq_info->irq[1].bitmap = bitmap1;
  48                 pirq_info->irq[2].link = link2;
  49                 pirq_info->irq[2].bitmap = bitmap2;
  50                 pirq_info->irq[3].link = link3;
  51                 pirq_info->irq[3].bitmap = bitmap3;
  52         pirq_info->slot = slot;
  53         pirq_info->rfu = rfu;
  54 }
  55 extern unsigned char bus_isa;
  56 extern unsigned char bus_sis966[8]; //1
  57
  58 extern void get_bus_conf(void);
  59
  60 unsigned long write_pirq_routing_table(unsigned long addr)
  61 {
  62
  63         struct irq_routing_table *pirq;
  64         struct irq_info *pirq_info;
  65         unsigned slot_num;
  66         uint8_t *v;
  67         unsigned sbdn;
  68
  69         uint8_t sum=0;
  70         int i;
  71
  72         get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
  73         sbdn = sysconf.sbdn;
  74
  75         /* Align the table to be 16 byte aligned. */
  76         addr += 15;
  77         addr &= ~15;
  78
  79         /* This table must be betweeen 0xf0000 & 0x100000 */
  80         printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr);
  81
  82         pirq = (void *)(addr);
  83         v = (uint8_t *)(addr);
  84
  85         pirq->signature = PIRQ_SIGNATURE;
  86         pirq->version  = PIRQ_VERSION;
  87
  88         pirq->rtr_bus = 0;
  89         pirq->rtr_devfn = PCI_DEVFN(2, 0);
  90
  91         pirq->exclusive_irqs = 0;
  92
  93         pirq->rtr_vendor = PCI_VENDOR_ID_SIS;
  94         pirq->rtr_device = PCI_DEVICE_ID_SIS_SIS966_LPC;
  95
  96         pirq->miniport_data = 0;
  97
  98         memset(pirq->rfu, 0, sizeof(pirq->rfu));
  99
 100         pirq_info = (void *) ( &pirq->checksum + 1);
 101         slot_num = 0;
 102
 103         write_pirq_info(pirq_info, 0, PCI_DEVFN(2, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
 104         pirq_info++; slot_num++;
 105
 106         pirq->size = 32 + 16 * slot_num;
 107
 108         for (i = 0; i < pirq->size; i++)
 109                 sum += v[i];
 110
 111         sum = pirq->checksum - sum;
 112
 113         if (sum != pirq->checksum) {
 114                 pirq->checksum = sum;
 115         }
 116
 117         printk(BIOS_INFO, "done.\n");
 118
 119         {
 120                 device_t dev;
 121                 dev = dev_find_slot(0, PCI_DEVFN(2,0));
 122                 if (dev) {
 123                         /* initialize PCI interupts - these assignments depend
 124                         on the PCB routing of PINTA-D
 125
 126                         PINTA = IRQ10
 127                         PINTB = IRQ11
 128                         PINTC = NA
 129                         PINTD = IRQ10
 130                         PINTE = IRQ11
 131                         PINTF = IRQ5
 132                         PINTG = NA
 133                         PINTH = IRQ7
 134
 135                         */
 136                 int     i;
 137                 uint8_t reg[8]={0x41,0x42,0x43,0x44,0x60,0x61,0x62,0x63};
 138                 uint8_t irq[8]={0x0A,0X0B,0X0,0X0a,0X0B,0X05,0X0,0X07};
 139
 140                 for(i=0;i<8;i++)
 141                     pci_write_config8(dev, reg[i], irq[i]);
 142                 } // endif
 143
 144                 printk(BIOS_DEBUG, "Setting Onboard SiS Southbridge\n");
 145
 146                 dev = dev_find_slot(0, PCI_DEVFN(2,5));   // 5513 (IDE)
 147                 pci_write_config8(dev, 0x3C, 0x0A);
 148                 dev = dev_find_slot(0, PCI_DEVFN(3,0));   // USB 1.1
 149                 pci_write_config8(dev, 0x3C, 0x0B);
 150                 dev = dev_find_slot(0, PCI_DEVFN(3,1));   // USB 1.1
 151                 pci_write_config8(dev, 0x3C, 0x05);
 152                 dev = dev_find_slot(0, PCI_DEVFN(3,3));   // USB 2.0
 153                 pci_write_config8(dev, 0x3C, 0x07);
 154                 dev = dev_find_slot(0, PCI_DEVFN(4,0));   // 191 (LAN)
 155                 pci_write_config8(dev, 0x3C, 0x0A);
 156                 dev = dev_find_slot(0, PCI_DEVFN(5,0));   // 1183 (SATA)
 157                 pci_write_config8(dev, 0x3C, 0x0B);
 158                 dev = dev_find_slot(0, PCI_DEVFN(6,0));   // PCI-E
 159                 pci_write_config8(dev, 0x3C, 0x0A);
 160                 dev = dev_find_slot(0, PCI_DEVFN(7,0));   // PCI-E
 161                 pci_write_config8(dev, 0x3C, 0x0A);
 162                 dev = dev_find_slot(0, PCI_DEVFN(15,0));  // Azalia
 163                 pci_write_config8(dev, 0x3C, 0x05);
 164         }
 165
 166         printk(BIOS_DEBUG, "pirq routing table, size=%d\n", pirq->size);
 167         for (i = 0; i < pirq->size; i+=4)
 168                 printk(BIOS_DEBUG, "%.2x%.2x%.2x%.2x\n", v[i+3],v[i+2],v[i+1],v[i]);
 169
 170         return  (unsigned long) pirq_info;
 171
 172 }