2 * This file is part of the LinuxBIOS project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
6 * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
7 * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
27 #define RAMINIT_SYSINFO 1
29 #define K8_ALLOCATE_IO_RANGE 1
30 //#define K8_SCAN_PCI_BUS 1
33 #define QRANK_DIMM_SUPPORT 1
35 #if CONFIG_LOGICAL_CPUS==1
36 #define SET_NB_CFG_54 1
39 //used by init_cpus and fidvid
40 #define K8_SET_FIDVID 1
41 //if we want to wait for core1 done before DQS training, set it to 0
42 #define K8_SET_FIDVID_CORE0_ONLY 1
44 #if K8_REV_F_SUPPORT == 1
45 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
48 #define DBGP_DEFAULT 7
51 #include <device/pci_def.h>
52 #include <device/pci_ids.h>
54 #include <device/pnp_def.h>
55 #include <arch/romcc_io.h>
56 #include <cpu/x86/lapic.h>
57 #include "option_table.h"
58 #include "pc80/mc146818rtc_early.c"
60 #if USE_FAILOVER_IMAGE==0
61 #include "pc80/serial.c"
62 #include "arch/i386/lib/console.c"
63 #if CONFIG_USBDEBUG_DIRECT
64 #include "southbridge/sis/sis966/sis966_enable_usbdebug_direct.c"
65 #include "pc80/usbdebug_direct_serial.c"
67 #include "ram/ramtest.c"
69 #include <cpu/amd/model_fxx_rev.h>
71 #include "southbridge/sis/sis966/sis966_early_smbus.c"
72 #include "southbridge/sis/sis966/sis966_enable_rom.c"
73 #include "northbridge/amd/amdk8/raminit.h"
74 #include "cpu/amd/model_fxx/apic_timer.c"
75 #include "lib/delay.c"
79 #include "cpu/x86/lapic/boot_cpu.c"
80 #include "northbridge/amd/amdk8/reset_test.c"
81 #include "superio/ite/it8716f/it8716f_early_serial.c"
82 #include "superio/ite/it8716f/it8716f_early_init.c"
84 #if USE_FAILOVER_IMAGE==0
86 #include "cpu/x86/bist.h"
88 #if CONFIG_USE_INIT == 0
89 #include "lib/memcpy.c"
92 #include "northbridge/amd/amdk8/debug.c"
94 #include "cpu/amd/mtrr/amd_earlymtrr.c"
96 #include "northbridge/amd/amdk8/setup_resource_map.c"
98 #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
100 #include "southbridge/sis/sis966/sis966_early_ctrl.c"
102 static void memreset_setup(void)
106 static void memreset(int controllers, const struct mem_controller *ctrl)
110 static inline void activate_spd_rom(const struct mem_controller *ctrl)
115 static inline int spd_read_byte(unsigned device, unsigned address)
117 return smbus_read_byte(device, address);
120 #include "northbridge/amd/amdk8/amdk8_f.h"
121 #include "northbridge/amd/amdk8/coherent_ht.c"
123 #include "northbridge/amd/amdk8/incoherent_ht.c"
125 #include "northbridge/amd/amdk8/raminit_f.c"
127 #include "sdram/generic_sdram.c"
129 #include "resourcemap.c"
131 #include "cpu/amd/dualcore/dualcore.c"
134 #define SIS966_USE_NIC 1
135 #define SIS966_USE_AZA 1
137 #define SIS966_PCI_E_X_0 0
139 #define SIS966_MB_SETUP \
140 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
141 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
142 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
143 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
144 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
145 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
147 #include "southbridge/sis/sis966/sis966_early_setup_ss.h"
148 #include "southbridge/sis/sis966/sis966_early_setup_car.c"
150 #include "cpu/amd/car/copy_and_run.c"
152 #include "cpu/amd/car/post_cache_as_ram.c"
154 #include "cpu/amd/model_fxx/init_cpus.c"
156 #include "cpu/amd/model_fxx/fidvid.c"
160 #if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
162 #include "southbridge/sis/sis966/sis966_enable_rom.c"
163 #include "northbridge/amd/amdk8/early_ht.c"
166 static void sio_setup(void)
173 byte = pci_read_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b);
175 pci_write_config8(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0x7b, byte);
177 dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0);
179 pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa0, dword);
181 dword = pci_read_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4);
183 pci_write_config32(PCI_DEV(0, SIS966_DEVN_BASE+1 , 0), 0xa4, dword);
186 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
188 unsigned last_boot_normal_x = last_boot_normal();
190 /* Is this a cpu only reset? or Is this a secondary cpu? */
191 if ((cpu_init_detectedx) || (!boot_cpu())) {
192 if (last_boot_normal_x) {
199 /* Nothing special needs to be done to find bus 0 */
200 /* Allow the HT devices to be found */
202 enumerate_ht_chain();
206 /* Setup the sis966 */
209 /* Is this a deliberate reset by the bios */
210 if (bios_reset_detected() && last_boot_normal_x) {
213 /* This is the primary cpu how should I boot? */
214 else if (do_normal_boot()) {
221 __asm__ volatile ("jmp __normal_image"
223 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
227 #if HAVE_FAILOVER_BOOT==1
228 __asm__ volatile ("jmp __fallback_image"
230 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
236 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
238 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
240 #if HAVE_FAILOVER_BOOT==1
241 #if USE_FAILOVER_IMAGE==1
242 failover_process(bist, cpu_init_detectedx);
244 real_main(bist, cpu_init_detectedx);
247 #if USE_FALLBACK_IMAGE == 1
248 failover_process(bist, cpu_init_detectedx);
250 real_main(bist, cpu_init_detectedx);
254 #if USE_FAILOVER_IMAGE==0
256 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
258 static const uint16_t spd_addr [] = {
259 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
260 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
261 #if CONFIG_MAX_PHYSICAL_CPUS > 1
262 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
263 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
267 struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
270 unsigned bsp_apicid = 0;
273 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
276 pnp_enter_ext_func_mode(SERIAL_DEV);
277 pnp_write_config(SERIAL_DEV, 0x23, 0);
278 it8716f_enable_dev(SERIAL_DEV, TTYS0_BASE);
279 pnp_exit_ext_func_mode(SERIAL_DEV);
281 setup_mb_resource_map();
285 /* Halt if there was a built in self test failure */
286 report_bist_failure(bist);
289 #if CONFIG_USBDEBUG_DIRECT
290 sis966_enable_usbdebug_direct(DBGP_DEFAULT);
291 early_usbdebug_direct_init();
294 print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
296 print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
298 #if MEM_TRAIN_SEQ == 1
299 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
301 setup_coherent_ht_domain(); // routing table and start other core0
303 wait_all_core0_started();
304 #if CONFIG_LOGICAL_CPUS==1
305 // It is said that we should start core1 after all core0 launched
306 /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
307 * So here need to make sure last core0 is started, esp for two way system,
308 * (there may be apic id conflicts in that case)
311 wait_all_other_cores_started(bsp_apicid);
314 /* it will set up chains and store link pair for optimization later */
315 ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
317 #if K8_SET_FIDVID == 1
321 msr=rdmsr(0xc0010042);
322 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
328 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
330 init_fidvid_bsp(bsp_apicid);
332 // show final fid and vid
335 msr=rdmsr(0xc0010042);
336 print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
341 needs_reset |= optimize_link_coherent_ht();
342 needs_reset |= optimize_link_incoherent_ht(sysinfo);
344 // fidvid change will issue one LDTSTOP and the HT change will be effective too
346 print_info("ht reset -\r\n");
349 allow_all_aps_stop(bsp_apicid);
351 //It's the time to set ctrl in sysinfo now;
352 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
359 //do we need apci timer, tsc...., only debug need it for better output
360 /* all ap stopped? */
361 // init_timer(); // Need to use TMICT to synconize FID/VID
363 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
366 post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now