2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 AMD
5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
6 ## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
7 ## Written by Morgan Tsai <my_tsai@sis.com> for SiS.
9 ## This program is free software; you can redistribute it and/or modify
10 ## it under the terms of the GNU General Public License as published by
11 ## the Free Software Foundation; either version 2 of the License, or
12 ## (at your option) any later version.
14 ## This program is distributed in the hope that it will be useful,
15 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ## GNU General Public License for more details.
19 ## You should have received a copy of the GNU General Public License
20 ## along with this program; if not, write to the Free Software
21 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 uses CONFIG_GENERATE_MP_TABLE
25 uses CONFIG_GENERATE_PIRQ_TABLE
26 uses CONFIG_GENERATE_ACPI_TABLES
27 uses CONFIG_HAVE_ACPI_RESUME
28 uses CONFIG_ACPI_SSDTX_NUM
29 uses CONFIG_USE_FALLBACK_IMAGE
30 uses CONFIG_USE_FAILOVER_IMAGE
31 uses CONFIG_HAVE_FALLBACK_BOOT
32 uses CONFIG_HAVE_FAILOVER_BOOT
33 uses CONFIG_HAVE_HARD_RESET
34 uses CONFIG_IRQ_SLOT_COUNT
35 uses CONFIG_HAVE_OPTION_TABLE
37 uses CONFIG_MAX_PHYSICAL_CPUS
38 uses CONFIG_LOGICAL_CPUS
41 uses CONFIG_FALLBACK_SIZE
42 uses CONFIG_FAILOVER_SIZE
44 uses CONFIG_ROM_SECTION_SIZE
45 uses CONFIG_ROM_IMAGE_SIZE
46 uses CONFIG_ROM_SECTION_SIZE
47 uses CONFIG_ROM_SECTION_OFFSET
48 uses CONFIG_ROM_PAYLOAD
49 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
50 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
51 uses CONFIG_PRECOMPRESSED_PAYLOAD
53 uses CONFIG_XIP_ROM_SIZE
54 uses CONFIG_XIP_ROM_BASE
55 uses CONFIG_STACK_SIZE
57 uses CONFIG_USE_OPTION_TABLE
58 uses CONFIG_LB_CKS_RANGE_START
59 uses CONFIG_LB_CKS_RANGE_END
60 uses CONFIG_LB_CKS_LOC
61 uses CONFIG_MAINBOARD_PART_NUMBER
62 uses CONFIG_MAINBOARD_VENDOR
64 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
65 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
66 uses COREBOOT_EXTRA_VERSION
68 uses CONFIG_TTYS0_BAUD
69 uses CONFIG_TTYS0_BASE
71 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
72 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
73 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
74 uses CONFIG_CONSOLE_SERIAL8250
75 uses CONFIG_HAVE_INIT_TIMER
78 uses CONFIG_CROSS_COMPILE
82 uses CONFIG_CONSOLE_VGA
83 uses CONFIG_USBDEBUG_DIRECT
84 uses CONFIG_PCI_ROM_RUN
85 uses CONFIG_HW_MEM_HOLE_SIZEK
86 uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
87 uses CONFIG_K8_HT_FREQ_1G_SUPPORT
89 uses CONFIG_HT_CHAIN_UNITID_BASE
90 uses CONFIG_HT_CHAIN_END_UNITID_BASE
91 uses CONFIG_SB_HT_CHAIN_ON_BUS0
92 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
94 uses CONFIG_USE_DCACHE_RAM
95 uses CONFIG_DCACHE_RAM_BASE
96 uses CONFIG_DCACHE_RAM_SIZE
97 uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
100 uses CONFIG_SERIAL_CPU_INIT
102 uses CONFIG_ENABLE_APIC_EXT_ID
103 uses CONFIG_APIC_ID_OFFSET
104 uses CONFIG_LIFT_BSP_APIC_ID
106 uses CONFIG_PCI_64BIT_PREF_MEM
108 uses CONFIG_LB_MEM_TOPK
110 uses CONFIG_AP_CODE_IN_CAR
112 uses CONFIG_MEM_TRAIN_SEQ
114 uses CONFIG_WAIT_BEFORE_CPUS_INIT
116 uses CONFIG_USE_PRINTK_IN_CAR
123 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
125 default CONFIG_ROM_SIZE=524288
126 #default CONFIG_ROM_SIZE=0x100000
129 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
133 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
135 default CONFIG_FAILOVER_SIZE=0x01000
138 default CONFIG_LB_MEM_TOPK=2048
141 ## Build code for the fallback boot
143 default CONFIG_HAVE_FALLBACK_BOOT=1
144 default CONFIG_HAVE_FAILOVER_BOOT=1
147 ## Build code to reset the motherboard from coreboot
149 default CONFIG_HAVE_HARD_RESET=1
152 ## Build code to export a programmable irq routing table
154 default CONFIG_GENERATE_PIRQ_TABLE=1
155 default CONFIG_IRQ_SLOT_COUNT=11
158 ## Build code to export an x86 MP table
159 ## Useful for specifying IRQ routing values
161 default CONFIG_GENERATE_MP_TABLE=0
163 ## ACPI tables will be included
164 default CONFIG_GENERATE_ACPI_TABLES=0
167 ## Build code to export a CMOS option table
169 default CONFIG_HAVE_OPTION_TABLE=1
172 ## Move the default coreboot cmos range off of AMD RTC registers
174 default CONFIG_LB_CKS_RANGE_START=49
175 default CONFIG_LB_CKS_RANGE_END=122
176 default CONFIG_LB_CKS_LOC=123
179 ## Build code for SMP support
180 ## Only worry about 2 micro processors
183 default CONFIG_MAX_CPUS=2
184 default CONFIG_MAX_PHYSICAL_CPUS=1
185 default CONFIG_LOGICAL_CPUS=1
187 #default CONFIG_SERIAL_CPU_INIT=0
189 default CONFIG_ENABLE_APIC_EXT_ID=0
190 default CONFIG_APIC_ID_OFFSET=0x10
191 default CONFIG_LIFT_BSP_APIC_ID=1
193 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
195 #default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
197 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
199 #default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
201 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
202 #default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
204 #Opteron K8 1G HT Support
205 default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
208 default CONFIG_CONSOLE_VGA=1
209 default CONFIG_PCI_ROM_RUN=1
211 #default CONFIG_USBDEBUG_DIRECT=0
213 #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
214 default CONFIG_HT_CHAIN_UNITID_BASE=0
216 #real SB Unit ID, default is 0x20, mean dont touch it at last
217 #default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
219 #make the SB HT chain on bus 0, default is not (0)
220 default CONFIG_SB_HT_CHAIN_ON_BUS0=2
222 #only offset for SB chain?, default is yes(1)
223 default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
225 #allow capable device use that above 4G
226 #default CONFIG_PCI_64BIT_PREF_MEM=1
229 ## enable CACHE_AS_RAM specifics
231 default CONFIG_USE_DCACHE_RAM=1
232 default CONFIG_DCACHE_RAM_BASE=0xc8000
233 default CONFIG_DCACHE_RAM_SIZE=0x08000
234 default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
235 default CONFIG_USE_INIT=0
237 default CONFIG_AP_CODE_IN_CAR=0
238 default CONFIG_MEM_TRAIN_SEQ=2
239 default CONFIG_WAIT_BEFORE_CPUS_INIT=0
242 ## Build code to setup a generic IOAPIC
244 default CONFIG_IOAPIC=1
247 ## Clean up the motherboard id strings
249 default CONFIG_MAINBOARD_PART_NUMBER="ga_2761gxdk"
250 default CONFIG_MAINBOARD_VENDOR="GIGABYTE"
251 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1039
252 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234
255 ### coreboot layout values
258 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
259 default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
262 ## Use a small 8K stack
264 default CONFIG_STACK_SIZE=0x2000
267 ## Use a small 32K heap
269 default CONFIG_HEAP_SIZE=0x8000
272 ## Only use the option table in a normal image
274 default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
277 ## Coreboot C code runs at this location in RAM
279 default CONFIG_RAMBASE=0x00100000
282 ## Load the payload from the ROM
284 default CONFIG_ROM_PAYLOAD = 1
286 #default CONFIG_COMPRESSED_PAYLOAD_NRV2B = 1
289 ### Defaults of options that you may want to override in the target config file
293 ## The default compiler
295 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
299 ## Disable the gdb stub by default
301 default CONFIG_GDB_STUB=0
304 ## The Serial Console
306 default CONFIG_USE_PRINTK_IN_CAR=1
308 # To Enable the Serial Console
309 default CONFIG_CONSOLE_SERIAL8250=1
311 ## Select the serial console baud rate
312 default CONFIG_TTYS0_BAUD=115200
313 #default CONFIG_TTYS0_BAUD=57600
314 #default CONFIG_TTYS0_BAUD=38400
315 #default CONFIG_TTYS0_BAUD=19200
316 #default CONFIG_TTYS0_BAUD=9600
317 #default CONFIG_TTYS0_BAUD=4800
318 #default CONFIG_TTYS0_BAUD=2400
319 #default CONFIG_TTYS0_BAUD=1200
321 # Select the serial console base port
322 default CONFIG_TTYS0_BASE=0x3f8
324 # Select the serial protocol
325 # This defaults to 8 data bits, 1 stop bit, and no parity
326 default CONFIG_TTYS0_LCS=0x3
329 ### Select the coreboot loglevel
331 ## EMERG 1 system is unusable
332 ## ALERT 2 action must be taken immediately
333 ## CRIT 3 critical conditions
334 ## ERR 4 error conditions
335 ## WARNING 5 warning conditions
336 ## NOTICE 6 normal but significant condition
337 ## INFO 7 informational
338 ## CONFIG_DEBUG 8 debug-level messages
339 ## SPEW 9 Way too many details
341 ## Request this level of debugging output
342 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
343 ## At a maximum only compile in this level of debugging
344 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
347 ## Select power on after power fail setting
348 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"