2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 AMD
5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
6 ## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
7 ## Written by Morgan Tsai <my_tsai@sis.com> for SiS.
9 ## This program is free software; you can redistribute it and/or modify
10 ## it under the terms of the GNU General Public License as published by
11 ## the Free Software Foundation; either version 2 of the License, or
12 ## (at your option) any later version.
14 ## This program is distributed in the hope that it will be useful,
15 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ## GNU General Public License for more details.
19 ## You should have received a copy of the GNU General Public License
20 ## along with this program; if not, write to the Free Software
21 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
25 default CONFIG_XIP_ROM_SIZE = 64 * 1024
26 include /config/failovercalculation.lb
31 ## Build the objects we have code for in this directory.
35 #needed by irq_tables and mptable and acpi_tables
38 if CONFIG_GENERATE_MP_TABLE object mptable.o end
39 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
42 makerule ./cache_as_ram_auto.o
43 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
44 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
47 makerule ./cache_as_ram_auto.inc
48 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
49 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_CPU_OPT) $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
50 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
51 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
55 if CONFIG_USE_FAILOVER_IMAGE
57 if CONFIG_AP_CODE_IN_CAR
59 depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
60 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
62 ldscript /arch/i386/init/ldscript_apc.lb
68 ## Build our 16 bit and 32 bit coreboot entry code
70 if CONFIG_HAVE_FAILOVER_BOOT
71 if CONFIG_USE_FAILOVER_IMAGE
72 mainboardinit cpu/x86/16bit/entry16.inc
73 ldscript /cpu/x86/16bit/entry16.lds
76 if CONFIG_USE_FALLBACK_IMAGE
77 mainboardinit cpu/x86/16bit/entry16.inc
78 ldscript /cpu/x86/16bit/entry16.lds
82 mainboardinit cpu/x86/32bit/entry32.inc
85 ldscript /cpu/x86/32bit/entry32.lds
89 ldscript /cpu/amd/car/cache_as_ram.lds
93 ## Build our reset vector (This is where coreboot is entered)
95 if CONFIG_HAVE_FAILOVER_BOOT
96 if CONFIG_USE_FAILOVER_IMAGE
97 mainboardinit cpu/x86/16bit/reset16.inc
98 ldscript /cpu/x86/16bit/reset16.lds
100 mainboardinit cpu/x86/32bit/reset32.inc
101 ldscript /cpu/x86/32bit/reset32.lds
104 if CONFIG_USE_FALLBACK_IMAGE
105 mainboardinit cpu/x86/16bit/reset16.inc
106 ldscript /cpu/x86/16bit/reset16.lds
108 mainboardinit cpu/x86/32bit/reset32.inc
109 ldscript /cpu/x86/32bit/reset32.lds
114 ## Include an id string (For safe flashing)
116 mainboardinit arch/i386/lib/id.inc
117 ldscript /arch/i386/lib/id.lds
120 ## ROMSTRAP table for MCP55
122 if CONFIG_HAVE_FAILOVER_BOOT
123 if CONFIG_USE_FAILOVER_IMAGE
124 mainboardinit southbridge/sis/sis966/romstrap.inc
125 ldscript /southbridge/sis/sis966/romstrap.lds
128 if CONFIG_USE_FALLBACK_IMAGE
129 mainboardinit southbridge/sis/sis966/romstrap.inc
130 ldscript /southbridge/sis/sis966/romstrap.lds
135 ## Setup Cache-As-Ram
137 mainboardinit cpu/amd/car/cache_as_ram.inc
140 ### This is the early phase of coreboot startup
141 ### Things are delicate and we test to see if we should
142 ### failover to another image.
144 if CONFIG_HAVE_FAILOVER_BOOT
145 if CONFIG_USE_FAILOVER_IMAGE
146 ldscript /arch/i386/lib/failover_failover.lds
149 if CONFIG_USE_FALLBACK_IMAGE
150 ldscript /arch/i386/lib/failover.lds
158 initobject cache_as_ram_auto.o
160 mainboardinit ./cache_as_ram_auto.inc
164 ## Include the secondary Configuration files
168 chip northbridge/amd/amdk8/root_complex
169 device apic_cluster 0 on
170 chip cpu/amd/socket_AM2
174 device pci_domain 0 on
175 chip northbridge/amd/amdk8 #mc0
177 # devices on link 0, link 0 == LDT 0
178 chip southbridge/sis/sis966
179 device pci 0.0 on end # Northbridge
180 device pci 1.0 on # AGP bridge
181 device pci 0.0 on end
183 device pci 2.0 on # LPC
184 chip superio/ite/it8716f
185 device pnp 2e.0 off # Floppy (N/A)
190 device pnp 2e.1 on # Com1
194 device pnp 2e.2 off # Com2 (N/A)
198 device pnp 2e.3 off # Parallel port (N/A)
202 device pnp 2e.4 on # EC
207 device pnp 2e.5 off # PS/2 keyboard (N/A)
212 device pnp 2e.6 off # Mouse (N/A)
215 device pnp 2e.8 off # MIDI (N/A)
219 device pnp 2e.9 off # GAME (N/A)
222 device pnp 2e.a off end # CIR (N/A)
226 device pci 2.5 off end # IDE (SiS5513)
227 device pci 2.6 off end # Modem (SiS7013)
228 device pci 2.7 off end # Audio (SiS7012)
229 device pci 3.0 on end # USB (SiS7001,USB1.1)
230 device pci 3.1 on end # USB (SiS7001,USB1.1)
231 device pci 3.3 on end # USB (SiS7002,USB2.0)
232 device pci 4.0 on end # NIC (SiS191)
233 device pci 5.0 on end # SATA (SiS1183,Native Mode)
234 device pci 6.0 on end # PCI-e x1
235 device pci 7.0 on end # PCI-e x1
236 device pci a.0 off end
237 device pci b.0 off end
238 device pci c.0 off end
239 device pci d.0 off end
240 device pci e.0 off end
241 device pci f.0 off end # HD Audio (SiS7502)
243 register "ide0_enable" = "1"
244 register "ide1_enable" = "1"
245 register "sata0_enable" = "1"
246 register "sata1_enable" = "1"
248 end # device pci 18.0
249 device pci 18.0 on end # Link 1
250 device pci 18.0 on end
251 device pci 18.1 on end
252 device pci 18.2 on end
253 device pci 18.3 on end
258 # chip drivers/generic/debug
259 # device pnp 0.0 off end # chip name
260 # device pnp 0.1 on end # pci_regs_all
261 # device pnp 0.2 off end # mem
262 # device pnp 0.3 off end # cpuid
263 # device pnp 0.4 off end # smbus_regs_all
264 # device pnp 0.5 off end # dual core msr
265 # device pnp 0.6 off end # cache size
266 # device pnp 0.7 off end # tsc
267 # device pnp 0.8 off end # io
268 # device pnp 0.9 off end # io