src/mainboard/gigabyte/ga_2761gxdk/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright (C) 2007 AMD
   5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6 ## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
   7 ## Written by Morgan Tsai <my_tsai@sis.com> for SiS.
   8 ##
   9 ## This program is free software; you can redistribute it and/or modify
  10 ## it under the terms of the GNU General Public License as published by
  11 ## the Free Software Foundation; either version 2 of the License, or
  12 ## (at your option) any later version.
  13 ##
  14 ## This program is distributed in the hope that it will be useful,
  15 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 ## GNU General Public License for more details.
  18 ##
  19 ## You should have received a copy of the GNU General Public License
  20 ## along with this program; if not, write to the Free Software
  21 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  22 ##
  23
  24 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
  25 default CONFIG_XIP_ROM_SIZE = 64 * 1024
  26 include /config/failovercalculation.lb
  27
  28 arch i386 end
  29
  30 ##
  31 ## Build the objects we have code for in this directory.
  32 ##
  33
  34 driver mainboard.o
  35 #needed by irq_tables and mptable and acpi_tables
  36 object get_bus_conf.o
  37
  38 if CONFIG_GENERATE_MP_TABLE object mptable.o end
  39 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
  40
  41         if CONFIG_USE_INIT
  42                 makerule ./cache_as_ram_auto.o
  43                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  44                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  45                 end
  46         else
  47                 makerule ./cache_as_ram_auto.inc
  48                         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  49                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_CPU_OPT) $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  50                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  51                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  52                 end
  53         end
  54
  55 if CONFIG_USE_FAILOVER_IMAGE
  56 else
  57     if CONFIG_AP_CODE_IN_CAR
  58         makerule ./apc_auto.o
  59                 depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
  60                 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
  61         end
  62         ldscript /arch/i386/init/ldscript_apc.lb
  63     end
  64 end
  65
  66
  67 ##
  68 ## Build our 16 bit and 32 bit coreboot entry code
  69 ##
  70 if CONFIG_HAVE_FAILOVER_BOOT
  71     if CONFIG_USE_FAILOVER_IMAGE
  72         mainboardinit cpu/x86/16bit/entry16.inc
  73         ldscript /cpu/x86/16bit/entry16.lds
  74     end
  75 else
  76     if CONFIG_USE_FALLBACK_IMAGE
  77         mainboardinit cpu/x86/16bit/entry16.inc
  78         ldscript /cpu/x86/16bit/entry16.lds
  79     end
  80 end
  81
  82 mainboardinit cpu/x86/32bit/entry32.inc
  83
  84         if CONFIG_USE_INIT
  85                 ldscript /cpu/x86/32bit/entry32.lds
  86         end
  87
  88         if CONFIG_USE_INIT
  89                 ldscript /cpu/amd/car/cache_as_ram.lds
  90         end
  91
  92 ##
  93 ## Build our reset vector (This is where coreboot is entered)
  94 ##
  95 if CONFIG_HAVE_FAILOVER_BOOT
  96     if CONFIG_USE_FAILOVER_IMAGE
  97         mainboardinit cpu/x86/16bit/reset16.inc
  98         ldscript /cpu/x86/16bit/reset16.lds
  99     else
 100         mainboardinit cpu/x86/32bit/reset32.inc
 101         ldscript /cpu/x86/32bit/reset32.lds
 102     end
 103 else
 104     if CONFIG_USE_FALLBACK_IMAGE
 105         mainboardinit cpu/x86/16bit/reset16.inc
 106         ldscript /cpu/x86/16bit/reset16.lds
 107     else
 108         mainboardinit cpu/x86/32bit/reset32.inc
 109         ldscript /cpu/x86/32bit/reset32.lds
 110     end
 111 end
 112
 113 ##
 114 ## Include an id string (For safe flashing)
 115 ##
 116 mainboardinit southbridge/sis/sis966/id.inc
 117 ldscript /southbridge/sis/sis966/id.lds
 118
 119 ##
 120 ## ROMSTRAP table for MCP55
 121 ##
 122 if CONFIG_HAVE_FAILOVER_BOOT
 123     if CONFIG_USE_FAILOVER_IMAGE
 124         mainboardinit southbridge/sis/sis966/romstrap.inc
 125         ldscript /southbridge/sis/sis966/romstrap.lds
 126     end
 127 else
 128     if CONFIG_USE_FALLBACK_IMAGE
 129         mainboardinit southbridge/sis/sis966/romstrap.inc
 130         ldscript /southbridge/sis/sis966/romstrap.lds
 131     end
 132 end
 133
 134         ##
 135         ## Setup Cache-As-Ram
 136         ##
 137         mainboardinit cpu/amd/car/cache_as_ram.inc
 138
 139 ###
 140 ### This is the early phase of coreboot startup
 141 ### Things are delicate and we test to see if we should
 142 ### failover to another image.
 143 ###
 144 if CONFIG_HAVE_FAILOVER_BOOT
 145     if CONFIG_USE_FAILOVER_IMAGE
 146                 ldscript /arch/i386/lib/failover_failover.lds
 147     end
 148 else
 149     if CONFIG_USE_FALLBACK_IMAGE
 150                 ldscript /arch/i386/lib/failover.lds
 151     end
 152 end
 153
 154 ##
 155 ## Setup RAM
 156 ##
 157         if CONFIG_USE_INIT
 158                 initobject cache_as_ram_auto.o
 159         else
 160                 mainboardinit ./cache_as_ram_auto.inc
 161         end
 162
 163 ##
 164 ## Include the secondary Configuration files
 165 ##
 166 config chip.h
 167
 168 chip northbridge/amd/amdk8/root_complex
 169         device apic_cluster 0 on
 170                 chip cpu/amd/socket_AM2
 171                         device apic 0 on end
 172                 end
 173         end
 174         device pci_domain 0 on
 175                 chip northbridge/amd/amdk8 #mc0
 176                         device pci 18.0 on
 177                                 #  devices on link 0, link 0 == LDT 0
 178                                 chip southbridge/sis/sis966
 179                                         device pci 0.0 on end   # Northbridge
 180                                         device pci 1.0 on               # AGP bridge
 181                                                 device pci 0.0 on end
 182                                         end
 183                                         device pci 2.0 on # LPC
 184                                                 chip superio/ite/it8716f
 185                                                         device pnp 2e.0 off #  Floppy (N/A)
 186                                                                 io 0x60 = 0x3f0
 187                                                                 irq 0x70 = 6
 188                                                                 drq 0x74 = 2
 189                                                         end
 190                                                         device pnp 2e.1 on #  Com1
 191                                                                 io 0x60 = 0x3f8
 192                                                                 irq 0x70 = 4
 193                                                         end
 194                                                         device pnp 2e.2 off #  Com2 (N/A)
 195                                                                 io 0x60 = 0x2f8
 196                                                                 irq 0x70 = 3
 197                                                         end
 198                                                         device pnp 2e.3 off #  Parallel port (N/A)
 199                                                                 io 0x60 = 0x378
 200                                                                 irq 0x70 = 7
 201                                                         end
 202                                                         device pnp 2e.4 on #  EC
 203                                                                 io 0x60 = 0x290
 204                                                                 io 0x62 = 0x230
 205                                                                 irq 0x70 = 9
 206                                                         end
 207                                                         device pnp 2e.5 off #  PS/2 keyboard (N/A)
 208                                                                 io 0x60 = 0x60
 209                                                                 io 0x62 = 0x64
 210                                                                 irq 0x70 = 1
 211                                                         end
 212                                                         device pnp 2e.6 off #  Mouse (N/A)
 213                                                                 irq 0x70 = 12
 214                                                         end
 215                                                         device pnp 2e.8 off #  MIDI (N/A)
 216                                                                 io 0x60 = 0x300
 217                                                                 irq 0x70 = 10
 218                                                         end
 219                                                         device pnp 2e.9 off #  GAME (N/A)
 220                                                                 io 0x60 = 0x220
 221                                                         end
 222                                                         device pnp 2e.a off end #  CIR (N/A)
 223                                                 end
 224                                         end
 225
 226                                         device pci 2.5 off end # IDE (SiS5513)
 227                                         device pci 2.6 off end # Modem (SiS7013)
 228                                         device pci 2.7 off end # Audio (SiS7012)
 229                                         device pci 3.0 on end # USB (SiS7001,USB1.1)
 230                                         device pci 3.1 on end # USB (SiS7001,USB1.1)
 231                                         device pci 3.3 on end # USB (SiS7002,USB2.0)
 232                                         device pci 4.0 on end # NIC (SiS191)
 233                                         device pci 5.0 on end # SATA (SiS1183,Native Mode)
 234                                         device pci 6.0 on end # PCI-e x1
 235                                         device pci 7.0 on end # PCI-e x1
 236                                         device pci a.0 off end
 237                                         device pci b.0 off end
 238                                         device pci c.0 off end
 239                                         device pci d.0 off end
 240                                         device pci e.0 off end
 241                                         device pci f.0 off end # HD Audio (SiS7502)
 242
 243                                         register "ide0_enable" = "1"
 244                                         register "ide1_enable" = "1"
 245                                         register "sata0_enable" = "1"
 246                                         register "sata1_enable" = "1"
 247                                 end
 248                         end #  device pci 18.0
 249                         device pci 18.0 on end # Link 1
 250                         device pci 18.0 on end
 251                         device pci 18.1 on end
 252                         device pci 18.2 on end
 253                         device pci 18.3 on end
 254                 end # mc0
 255
 256         end # PCI domain
 257
 258 #       chip drivers/generic/debug
 259 #               device pnp 0.0 off end # chip name
 260 #               device pnp 0.1 on end # pci_regs_all
 261 #               device pnp 0.2 off end # mem
 262 #               device pnp 0.3 off end # cpuid
 263 #               device pnp 0.4 off end # smbus_regs_all
 264 #               device pnp 0.5 off end # dual core msr
 265 #               device pnp 0.6 off end # cache size
 266 #               device pnp 0.7 off end # tsc
 267 #               device pnp 0.8 off end # io
 268 #               device pnp 0.9 off end # io
 269 #       end
 270 end #root_complex