2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2008 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 #include <device/device.h>
23 #include <device/pci.h>
24 #include <console/console.h>
25 #include <arch/smp/mpspec.h>
26 #include <arch/ioapic.h>
30 static void *smp_write_config_table(void *v)
32 struct mp_config_table *mc;
34 int max_pci_bus, isa_bus;
36 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
38 mptable_init(mc, "P470 ", LAPIC_ADDR);
40 smp_write_processors(mc);
42 max_pci_bus = 5; // XXX read me from bridges.
45 isa_bus = max_pci_bus + 1;
47 /* Bus: Bus ID Type */
48 for (i=0; i <= max_pci_bus; i++)
49 smp_write_bus(mc, i, "PCI ");
51 smp_write_bus(mc, isa_bus, "ISA ");
53 /* I/O APICs: APIC ID Version State Address */
54 smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
56 /* Legacy Interrupts */
57 mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
59 /* Builtin devices on Bus 0 */
60 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10);
61 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13);
62 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17);
63 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13);
64 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12);
65 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10);
66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10);
67 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10);
68 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11);
71 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10);
73 // riser slot top 5:8.0
74 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14);
75 // riser slot middle 5:9.0
76 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15);
77 // riser slot bottom 5:a.0
78 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16);
80 /* Onboard Ethernet */
81 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10);
83 /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
84 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
85 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
87 /* Compute the checksums */
88 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
89 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
91 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
93 return smp_next_mpe_entry(mc);
96 unsigned long write_smp_table(unsigned long addr)
99 v = smp_write_floating_table(addr);
100 return (unsigned long)smp_write_config_table(v);