1 #include <console/console.h>
3 #include <arch/ioapic.h>
5 #include <device/device.h>
6 #include <device/pci.h>
14 #if CONFIG_WRITE_HIGH_TABLES==1
18 #define CMOS_ADDR_PORT 0x70
19 #define CMOS_DATA_PORT 0x71
20 #define HIGH_RAM_ADDR 0x35
21 #define LOW_RAM_ADDR 0x34
23 static unsigned long qemu_get_memory_size(void)
26 outb (HIGH_RAM_ADDR, CMOS_ADDR_PORT);
27 tomk = ((unsigned long) inb(CMOS_DATA_PORT)) << 14;
28 outb (LOW_RAM_ADDR, CMOS_ADDR_PORT);
29 tomk |= ((unsigned long) inb(CMOS_DATA_PORT)) << 6;
34 static void cpu_pci_domain_set_resources(device_t dev)
36 u32 pci_tolm = find_pci_tolm(dev->link_list);
37 unsigned long tomk = 0, tolmk;
40 tomk = qemu_get_memory_size();
41 printk(BIOS_DEBUG, "Detected %lu Kbytes (%lu MiB) RAM.\n",
44 /* Compute the top of Low memory */
45 tolmk = pci_tolm >> 10;
47 /* The PCI hole does not overlap the memory. */
51 /* Report the memory regions. */
53 ram_resource(dev, idx++, 0, 640);
54 ram_resource(dev, idx++, 768, tolmk - 768);
56 #if CONFIG_WRITE_HIGH_TABLES==1
57 /* Leave some space for ACPI, PIRQ and MP tables */
58 high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
59 high_tables_size = HIGH_MEMORY_SIZE;
62 assign_resources(dev->link_list);
65 static void cpu_pci_domain_read_resources(struct device *dev)
69 pci_domain_read_resources(dev);
71 /* Reserve space for the IOAPIC. This should be in the Southbridge,
72 * but I couldn't tell which device to put it in. */
73 res = new_resource(dev, 2);
74 res->base = IO_APIC_ADDR;
75 res->size = 0x100000UL;
76 res->limit = 0xffffffffUL;
77 res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
80 /* Reserve space for the LAPIC. There's one in every processor, but
81 * the space only needs to be reserved once, so we do it here. */
82 res = new_resource(dev, 3);
83 res->base = 0xfee00000UL;
84 res->size = 0x10000UL;
85 res->limit = 0xffffffffUL;
86 res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
90 #if CONFIG_GENERATE_SMBIOS_TABLES
91 static int qemu_get_smbios_data16(int handle, unsigned long *current)
93 struct smbios_type16 *t = (struct smbios_type16 *)*current;
94 int len = sizeof(struct smbios_type16);
96 memset(t, 0, sizeof(struct smbios_type16));
97 t->type = SMBIOS_PHYS_MEMORY_ARRAY;
100 t->location = 3; /* Location: System Board */
101 t->use = 3; /* System memory */
102 t->memory_error_correction = 3; /* No error correction */
103 t->maximum_capacity = qemu_get_memory_size();
108 static int qemu_get_smbios_data17(int handle, int parent_handle, unsigned long *current)
110 struct smbios_type17 *t = (struct smbios_type17 *)*current;
113 memset(t, 0, sizeof(struct smbios_type17));
114 t->type = SMBIOS_MEMORY_DEVICE;
116 t->phys_memory_array_handle = parent_handle;
117 t->length = sizeof(struct smbios_type17) - 2;
118 t->size = qemu_get_memory_size() / 1024;
121 t->form_factor = 9; /* DIMM */
122 t->device_locator = smbios_add_string(t->eos, "Virtual");
123 t->memory_type = 0x12; /* DDR */
124 t->type_detail = 0x80; /* Synchronous */
126 t->clock_speed = 200;
127 t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR);
128 len = t->length + smbios_string_table_len(t->eos);
133 static int qemu_get_smbios_data(device_t dev, int *handle, unsigned long *current)
136 len = qemu_get_smbios_data16(*handle, current);
137 len += qemu_get_smbios_data17(*handle+1, *handle, current);
142 static struct device_operations pci_domain_ops = {
143 .read_resources = cpu_pci_domain_read_resources,
144 .set_resources = cpu_pci_domain_set_resources,
145 .enable_resources = NULL,
147 .scan_bus = pci_domain_scan_bus,
148 #if CONFIG_GENERATE_SMBIOS_TABLES
149 .get_smbios_data = qemu_get_smbios_data,
153 static void enable_dev(struct device *dev)
155 /* Set the operations if it is a special bus type */
156 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
157 dev->ops = &pci_domain_ops;
162 struct chip_operations mainboard_emulation_qemu_x86_ops = {
163 CHIP_NAME("QEMU Northbridge")
164 .enable_dev = enable_dev,