2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2010 Anders Jenbo <anders@jenbo.dk>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 chip northbridge/intel/i82810 # Northbridge
22 device lapic_cluster 0 on # APIC cluster
23 chip cpu/intel/socket_PGA370 # CPU
24 device lapic 0 on end # APIC
27 device pci_domain 0 on # PCI domain
28 device pci 0.0 on end # Graphics Memory Controller Hub (GMCH)
29 device pci 1.0 on end # Chipset Graphics Controller (CGC)
30 chip southbridge/intel/i82801ax # Southbridge
31 register "ide0_enable" = "1"
32 register "ide1_enable" = "1"
34 device pci 1e.0 on end # PCI bridge
35 device pci 1f.0 on # ISA bridge
36 chip superio/ite/it8712f # Super I/O
37 device pnp 2e.0 off # Floppy
42 device pnp 2e.1 on # Com1
46 device pnp 2e.2 on # Com2
50 device pnp 2e.3 on # Parallel port
54 device pnp 2e.4 on # EC
59 device pnp 2e.5 on # PS/2 keyboard
64 device pnp 2e.6 on # PS/2 mouse
67 device pnp 2e.7 on # GPIO
71 device pnp 2e.8 off # MIDI
75 device pnp 2e.9 off # Game port
78 device pnp 2e.a off end # CIR
81 device pci 1f.1 on end # IDE
82 device pci 1f.2 on end # USB
83 device pci 1f.3 on end # SMBus