src/mainboard/eaglelion/5bcm/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <arch/hlt.h>
   7 #include <stdlib.h>
   8 #include <console/console.h>
   9 #include "lib/ramtest.c"
  10 //#include "southbridge/intel/i440bx/i440bx_early_smbus.c"
  11 #include "superio/nsc/pc97317/pc97317_early_serial.c"
  12 //#include "northbridge/intel/i440bx/raminit.h"
  13 #include "cpu/x86/bist.h"
  14 #include "southbridge/amd/cs5530/cs5530_enable_rom.c"
  15
  16 #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
  17
  18 //#include "lib/delay.c"
  19
  20 #include "northbridge/amd/gx1/raminit.c"
  21
  22 static void main(unsigned long bist)
  23 {
  24         pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  25         uart_init();
  26         console_init();
  27
  28         /* Halt if there was a built in self test failure */
  29         report_bist_failure(bist);
  30
  31         cs5530_enable_rom();
  32
  33         sdram_init();
  34
  35         /* Check all of memory */
  36 #if 0
  37         ram_check(0x00000000, msr.lo);
  38 #endif
  39 #if 0
  40         static const struct {
  41                 unsigned long lo, hi;
  42         } check_addrs[] = {
  43                 /* Check 16MB of memory @ 0*/
  44                 { 0x00000000, 0x01000000 },
  45 #if TOTAL_CPUS > 1
  46                 /* Check 16MB of memory @ 2GB */
  47                 { 0x80000000, 0x81000000 },
  48 #endif
  49         };
  50         int i;
  51         for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
  52                 ram_check(check_addrs[i].lo, check_addrs[i].hi);
  53         }
  54 #endif
  55 }
  56