src/mainboard/eaglelion/5bcm/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <arch/hlt.h>
   7 #include <stdlib.h>
   8 #include <console/console.h>
   9 #include "lib/ramtest.c"
  10 #include "superio/nsc/pc97317/pc97317_early_serial.c"
  11 #include "cpu/x86/bist.h"
  12 #include "southbridge/amd/cs5530/cs5530_enable_rom.c"
  13 #include "northbridge/amd/gx1/raminit.c"
  14
  15 #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
  16
  17 static void main(unsigned long bist)
  18 {
  19         pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  20         uart_init();
  21         console_init();
  22
  23         /* Halt if there was a built in self test failure */
  24         report_bist_failure(bist);
  25
  26         cs5530_enable_rom();
  27
  28         sdram_init();
  29
  30         /* Check all of memory */
  31 #if 0
  32         ram_check(0x00000000, msr.lo);
  33 #endif
  34 #if 0
  35         static const struct {
  36                 unsigned long lo, hi;
  37         } check_addrs[] = {
  38                 /* Check 16MB of memory @ 0*/
  39                 { 0x00000000, 0x01000000 },
  40 #if TOTAL_CPUS > 1
  41                 /* Check 16MB of memory @ 2GB */
  42                 { 0x80000000, 0x81000000 },
  43 #endif
  44         };
  45         int i;
  46         for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
  47                 ram_check(check_addrs[i].lo, check_addrs[i].hi);
  48         }
  49 #endif
  50 }