2 #include <device/pci_def.h>
4 #include <device/pnp_def.h>
5 #include <arch/romcc_io.h>
8 #include "pc80/udelay_io.c"
9 #include <pc80/mc146818rtc.h>
10 #include <console/console.h>
11 #include "southbridge/intel/i82801dx/i82801dx.h"
12 #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
13 #include "northbridge/intel/i855/raminit.h"
14 #include "northbridge/intel/i855/debug.c"
15 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
16 #include "cpu/x86/mtrr/earlymtrr.c"
17 #include "cpu/x86/bist.h"
20 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
22 static inline int spd_read_byte(unsigned device, unsigned address)
24 return smbus_read_byte(device, address);
27 #include "northbridge/intel/i855/raminit.c"
28 #include "northbridge/intel/i855/reset_test.c"
29 #include "lib/generic_sdram.c"
31 void main(unsigned long bist)
33 static const struct mem_controller memctrl[] = {
35 .d0 = PCI_DEV(0, 0, 1),
36 .channel0 = { DIMM0, 0 },
47 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
51 /* Halt if there was a built in self test failure */
52 report_bist_failure(bist);
58 if(!bios_reset_detected()) {
61 dump_spd_registers(&memctrl[0]);
62 dump_smbus_registers();
65 sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
71 dump_pci_device(PCI_DEV(0, 0, 0));
73 // Check all of memory
74 ram_check(0x00000000, msr.lo+(msr.hi<<32));
75 // Check 16MB of memory @ 0
76 ram_check(0x00000000, 0x01000000);
77 // Check 16MB of memory @ 2GB
78 ram_check(0x80000000, 0x81000000);