Move "select CACHE_AS_RAM" lines from boards into CPU socket.
[coreboot.git] / src / mainboard / digitallogic / adl855pc / Kconfig
1 if BOARD_DIGITALLOGIC_ADL855PC
2
3 config BOARD_SPECIFIC_OPTIONS # dummy
4         def_bool y
5         select ARCH_X86
6         select CPU_INTEL_SOCKET_MPGA479M
7         select NORTHBRIDGE_INTEL_I855
8         select SOUTHBRIDGE_INTEL_I82801DX
9         select SUPERIO_WINBOND_W83627HF
10         select HAVE_OPTION_TABLE
11         select HAVE_PIRQ_TABLE
12         select HAVE_HARD_RESET
13         select BOARD_ROMSIZE_KB_1024
14         select TINY_BOOTBLOCK
15
16 config MAINBOARD_DIR
17         string
18         default digitallogic/adl855pc
19
20 config MAINBOARD_PART_NUMBER
21         string
22         default "smartModule855"
23
24 config DCACHE_RAM_BASE
25         hex
26         default 0xffdf8000
27
28 config DCACHE_RAM_SIZE
29         hex
30         default 0x8000
31
32 config IRQ_SLOT_COUNT
33         int
34         default 5
35
36 endif # BOARD_DIGITALLOGIC_ADL855PC