src/mainboard/digitallogic/adl855pc/Config.lb

   1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
   2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
   3 include /config/nofailovercalculation.lb
   4
   5 ##
   6 ## Set all of the defaults for an x86 architecture
   7 ##
   8
   9 arch i386 end
  10
  11 ##
  12 ## Build the objects we have code for in this directory.
  13 ##
  14
  15 driver mainboard.o
  16 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
  17
  18 ##
  19 ## Romcc output
  20 ##
  21 makerule ./failover.E
  22         depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
  23         action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
  24 end
  25
  26 makerule ./failover.inc
  27         depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
  28         action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
  29 end
  30
  31 makerule ./auto.E
  32         depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
  33         action  "../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
  34 end
  35 makerule ./auto.inc
  36         depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
  37         action  "../romcc    -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
  38 end
  39
  40 ##
  41 ## Build our 16 bit and 32 bit coreboot entry code
  42 ##
  43 mainboardinit cpu/x86/16bit/entry16.inc
  44 mainboardinit cpu/x86/32bit/entry32.inc
  45 ldscript /cpu/x86/16bit/entry16.lds
  46 ldscript /cpu/x86/32bit/entry32.lds
  47
  48 ##
  49 ## Build our reset vector (This is where coreboot is entered)
  50 ##
  51 if CONFIG_USE_FALLBACK_IMAGE
  52         mainboardinit cpu/x86/16bit/reset16.inc
  53         ldscript /cpu/x86/16bit/reset16.lds
  54 else
  55         mainboardinit cpu/x86/32bit/reset32.inc
  56         ldscript /cpu/x86/32bit/reset32.lds
  57 end
  58
  59 ### Should this be in the northbridge code?
  60 mainboardinit arch/i386/lib/cpu_reset.inc
  61
  62 ##
  63 ## Include an id string (For safe flashing)
  64 ##
  65 mainboardinit arch/i386/lib/id.inc
  66 ldscript /arch/i386/lib/id.lds
  67
  68 ###
  69 ### This is the early phase of coreboot startup
  70 ### Things are delicate and we test to see if we should
  71 ### failover to another image.
  72 ###
  73 if CONFIG_USE_FALLBACK_IMAGE
  74         ldscript /arch/i386/lib/failover.lds
  75         mainboardinit ./failover.inc
  76 end
  77
  78 ###
  79 ### O.k. We aren't just an intermediary anymore!
  80 ###
  81
  82 ##
  83 ## Setup RAM
  84 ##
  85 mainboardinit cpu/x86/fpu_enable.inc
  86 mainboardinit cpu/x86/sse_enable.inc
  87 mainboardinit ./auto.inc
  88 mainboardinit cpu/x86/sse_disable.inc
  89 mainboardinit cpu/x86/mmx_disable.inc
  90
  91 ##
  92 ## Include the secondary Configuration files
  93 ##
  94 dir /pc80
  95 config chip.h
  96
  97 ## This does not look right but it is a literal conversion of the
  98 ## old version of this file.
  99 chip northbridge/intel/i855pm
 100         device pci_domain 0 on
 101                 device pci 0.0 on end
 102                 device pci 1.0 on end
 103                 chip southbridge/intel/i82801dbm
 104 #                       pci 11.0 on end
 105 #                       pci 11.1 on end
 106 #                       pci 11.2 on end
 107 #                       pci 11.3 on end
 108 #                       pci 11.4 on end
 109 #                       pci 11.5 on end
 110 #                       pci 11.6 on end
 111 #                       pci 12.0 on end
 112                         register "enable_usb" = "0"
 113                         register "enable_native_ide" = "0"
 114                         register "enable_usb" = "0"
 115                         register "enable_native_ide" = "0"
 116                         chip superio/winbond/w83627hf # link 1
 117                                 device pnp 2e.0 on      #  Floppy
 118                                          io 0x60 = 0x3f0
 119                                         irq 0x70 = 6
 120                                         drq 0x74 = 2
 121                                 end
 122                                 device pnp 2e.1 off     #  Parallel Port
 123                                          io 0x60 = 0x378
 124                                         irq 0x70 = 7
 125                                 end
 126                                 device pnp 2e.2 on      #  Com1
 127                                          io 0x60 = 0x3f8
 128                                         irq 0x70 = 4
 129                                 end
 130                                 device pnp 2e.3 off     #  Com2
 131                                         io 0x60 = 0x2f8
 132                                         irq 0x70 = 3
 133                                 end
 134                                 device pnp 2e.5 on      #  Keyboard
 135                                          io 0x60 = 0x60
 136                                          io 0x62 = 0x64
 137                                         irq 0x70 = 1
 138                                         irq 0x72 = 12
 139                                 end
 140                                 device pnp 2e.6 off end #  CIR
 141                                 device pnp 2e.7 off end #  GAME_MIDI_GIPO1
 142                                 device pnp 2e.8 off end #  GPIO2
 143                                 device pnp 2e.9 off end #  GPIO3
 144                                 device pnp 2e.a off end #  ACPI
 145                                 device pnp 2e.b on      #  HW Monitor
 146                                          io 0x60 = 0x290
 147                                 end
 148                                 register "com1" = "{1}"
 149                         #       register "com1" = "{1, 0, 0x3f8, 4}"
 150                         #       register "lpt" = "{1}"
 151                         end
 152                 end
 153         end
 154         device apic_cluster 0 on
 155                 chip cpu/intel/socket_mPGA479M
 156                         device apic 0 on end
 157                 end
 158         end
 159 end