src/mainboard/dell/s1850/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include <console/console.h>
   9 #include "lib/ramtest.c"
  10 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
  11 #include "northbridge/intel/e7520/raminit.h"
  12 #include "superio/nsc/pc8374/pc8374_early_init.c"
  13 #include "cpu/x86/lapic/boot_cpu.c"
  14 #include "cpu/x86/mtrr/earlymtrr.c"
  15 #include "debug.c"
  16 #include "watchdog.c"
  17 // Remove comment if resets in this file are actually used.
  18 // #include "reset.c"
  19 #include "s1850_fixups.c"
  20 #include "northbridge/intel/e7520/memory_initialized.c"
  21 #include "cpu/x86/bist.h"
  22 #include <spd.h>
  23
  24 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC8374_SP1)
  25
  26 #define DEVPRES_CONFIG  ( \
  27         DEVPRES_D0F0 | \
  28         DEVPRES_D1F0 | \
  29         DEVPRES_D2F0 | \
  30         DEVPRES_D3F0 | \
  31         DEVPRES_D4F0 | \
  32         DEVPRES_D6F0 | \
  33         0 )
  34 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  35
  36 static inline int spd_read_byte(unsigned device, unsigned address)
  37 {
  38         return smbus_read_byte(device, address);
  39 }
  40
  41 #include "northbridge/intel/e7520/raminit.c"
  42 #include "lib/generic_sdram.c"
  43
  44 /* IPMI garbage. This is all test stuff, if it really works we'll move it somewhere
  45  */
  46
  47 #define nftransport  0xc
  48
  49 #define OBF  0
  50 #define IBF 1
  51
  52 #define ipmidata  0xca0
  53 #define ipmicsr  0xca4
  54
  55 static inline void  ibfzero(void)
  56 {
  57         while(inb(ipmicsr) &  (1<<IBF))
  58                 ;
  59 }
  60 static inline void  clearobf(void)
  61 {
  62         (void) inb(ipmidata);
  63 }
  64
  65 static inline void  waitobf(void)
  66 {
  67         while((inb(ipmicsr) &  (1<<OBF)) == 0)
  68                 ;
  69 }
  70 /* quite possibly the stupidest interface ever designed. */
  71 static inline void  first_cmd_byte(unsigned char byte)
  72 {
  73         ibfzero();
  74         clearobf();
  75         outb(0x61, ipmicsr);
  76         ibfzero();
  77         clearobf();
  78         outb(byte, ipmidata);
  79 }
  80
  81 static inline void  next_cmd_byte(unsigned char byte)
  82 {
  83
  84         ibfzero();
  85         clearobf();
  86         outb(byte, ipmidata);
  87 }
  88
  89 static inline void  last_cmd_byte(unsigned char byte)
  90 {
  91         outb(0x62, ipmicsr);
  92
  93         ibfzero();
  94         clearobf();
  95         outb(byte,  ipmidata);
  96 }
  97
  98 static inline void read_response_byte(void)
  99 {
 100         int val = -1;
 101         if ((inb(ipmicsr)>>6) != 1)
 102                 return;
 103
 104         ibfzero();
 105         waitobf();
 106         val = inb(ipmidata);
 107         outb(0x68, ipmidata);
 108
 109         /* see if it is done */
 110         if ((inb(ipmicsr)>>6) != 1){
 111                 /* wait for the dummy read. Which describes this protocol */
 112                 waitobf();
 113                 (void)inb(ipmidata);
 114         }
 115 }
 116
 117 static inline void ipmidelay(void)
 118 {
 119         int i;
 120         for(i = 0; i < 1000; i++) {
 121                 inb(0x80);
 122         }
 123 }
 124
 125 static inline void bmc_foad(void)
 126 {
 127         unsigned char c;
 128         /* be safe; make sure it is really ready */
 129         while ((inb(ipmicsr)>>6)) {
 130                 outb(0x60, ipmicsr);
 131                 inb(ipmidata);
 132         }
 133         first_cmd_byte(nftransport << 2);
 134         ipmidelay();
 135         next_cmd_byte(0x12);
 136         ipmidelay();
 137         next_cmd_byte(2);
 138         ipmidelay();
 139         last_cmd_byte(3);
 140         ipmidelay();
 141 }
 142
 143 /* end IPMI garbage */
 144
 145 #include "arch/i386/lib/stages.c"
 146
 147 static void main(unsigned long bist)
 148 {
 149         u8 b;
 150         u16 w;
 151         u32 l;
 152         int do_reset;
 153
 154         static const struct mem_controller mch[] = {
 155                 {
 156                         .node_id = 0,
 157                         /*
 158                         .f0 = PCI_DEV(0, 0x00, 0),
 159                         .f1 = PCI_DEV(0, 0x00, 1),
 160                         .f2 = PCI_DEV(0, 0x00, 2),
 161                         .f3 = PCI_DEV(0, 0x00, 3),
 162                         */
 163                         /* the wiring on this part is really messed up */
 164                         /* this is my best guess so far */
 165                         .channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, },
 166                         .channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, },
 167                 }
 168         };
 169
 170         /* superio setup */
 171         /* observed from serialice */
 172         static const u8 earlyinit[] = {
 173                 0x21, 0x11, 0x11,
 174                 0x22, 1, 1,
 175                 0x23, 05, 05,
 176                 0x24, 0x81, 0x81,
 177                 0x26, 0, 0,
 178                 0,
 179         };
 180
 181         /* using SerialICE, we've seen this basic reset sequence on the dell.
 182          * we don't understand it as it uses undocumented registers, but
 183          * we're going to clone it.
 184          */
 185         /* enable a hidden device. */
 186         b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
 187         b |= 0x8;
 188         pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
 189
 190         /* read-write lock in CMOS on LPC bridge on ICH5 */
 191         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, 4);
 192
 193         /* operate on undocumented device */
 194         l = pci_read_config32(PCI_DEV(0, 0, 2), 0xa4);
 195         l |= 0x1000;
 196         pci_write_config32(PCI_DEV(0, 0, 2), 0xa4, l);
 197
 198         l = pci_read_config32(PCI_DEV(0, 0, 2), 0x9c);
 199         l |= 0x8000;
 200         pci_write_config32(PCI_DEV(0, 0, 2), 0x9c, l);
 201
 202         /* disable undocumented device */
 203         b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
 204         b &= ~0x8;
 205         pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
 206
 207         /* set up LPC bridge bits, some of which reply on undocumented
 208          * registers
 209          */
 210
 211         b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd8);
 212         b |= 4;
 213         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, b);
 214
 215         b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd4);
 216         b |= 2;
 217         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, b);
 218
 219         /* ACPI base address */
 220         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x40, 0x800);
 221
 222         /* Enable specific ACPI features */
 223         b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0x44);
 224         b |= 0x10;
 225         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, b);
 226
 227         /* ACPI control */
 228         w = inw(0x868);
 229         outw(w|0x800, 0x868);
 230         w = inw(0x866);
 231         outw(w|2, 0x866);
 232
 233 #if 0
 234         /*seriaice shows
 235         dell does this so leave it here so I don't forget
 236          */
 237         /* SMBUS */
 238         pci_write_config16(PCI_DEV(0, 0x1f, 3), 0x20, 0x08c0);
 239
 240         /* unknown */
 241         b = inb(0x8c2);
 242         outb(0xdf, 0x8c2);
 243 #endif
 244
 245         /* another device enable? */
 246         b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
 247         b |= 2;
 248         pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
 249
 250         /* ?? */
 251         l = pci_read_config32(PCI_DEV(0, 8, 0), 0xc0);
 252         do_reset = l & 0x8000000;
 253         l |= 0x8000000;
 254         pci_write_config32(PCI_DEV(0, 8, 0), 0xc0, l);
 255
 256         if (! do_reset) {
 257                 outb(2, 0xcf9);
 258                 outb(6, 0xcf9);
 259         }
 260         if (bist == 0) {
 261                 /* Skip this if there was a built in self test failure */
 262                 early_mtrr_init();
 263                 if (memory_initialized()) {
 264                         skip_romstage();
 265                 }
 266         }
 267         /* Setup the console */
 268         mainboard_set_ich5();
 269         //bmc_foad();
 270         pc8374_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
 271         uart_init();
 272         console_init();
 273
 274         /* stuff we seem to need */
 275         pc8374_enable_dev(PNP_DEV(0x2e, PC8374_KBCK), 0);
 276
 277         /* GPIOs */
 278         pc8374_enable_dev(PNP_DEV(0x2e, PC8374_GPIO), 0xc20);
 279
 280         /* keep this in mind.
 281         SerialICE-hlp: outb 002e <= 23
 282         SerialICE-hlp:  inb 002f => 05
 283         SerialICE-hlp: outb 002f <= 05
 284         SerialICE-hlp: outb 002e <= 24
 285         SerialICE-hlp:  inb 002f => c1
 286         SerialICE-hlp: outb 002f <= c1
 287          */
 288
 289         /* Halt if there was a built in self test failure */
 290 //      report_bist_failure(bist);
 291
 292         /* MOVE ME TO A BETTER LOCATION !!! */
 293         /* config LPC decode for flash memory access */
 294         device_t dev;
 295         dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
 296         if (dev == PCI_DEV_INVALID) {
 297                 die("Missing ich5?");
 298         }
 299         pci_write_config32(dev, 0xe8, 0x00000000);
 300         pci_write_config8(dev, 0xf0, 0x00);
 301
 302 #if 0
 303         display_cpuid_update_microcode();
 304 #endif
 305 #if 1
 306         print_pci_devices();
 307 #endif
 308 #if 1
 309         enable_smbus();
 310 #endif
 311 #if 0
 312 //      dump_spd_registers(&cpu[0]);
 313         int i;
 314         for(i = 0; i < 1; i++) {
 315                 dump_spd_registers();
 316         }
 317 #endif
 318 #if 1
 319         show_dram_slots();
 320 #endif
 321         disable_watchdogs();
 322 //      dump_ipmi_registers();
 323         mainboard_set_e7520_leds();
 324
 325         sdram_initialize(ARRAY_SIZE(mch), mch);
 326 #if 0
 327         dump_pci_devices();
 328 #endif
 329 #if 1
 330         dump_pci_device(PCI_DEV(0, 0x00, 0));
 331 //      dump_bar14(PCI_DEV(0, 0x00, 0));
 332 #endif
 333
 334 #if 1 // temporarily disabled
 335         /* Check the first 1M */
 336 //      ram_check(0x00000000, 0x000100000);
 337 //      ram_check(0x00000000, 0x000a0000);
 338 //      ram_check(0x00100000, 0x01000000);
 339         ram_check(0x00100000, 0x00100100);
 340         /* check the first 1M in the 3rd Gig */
 341 //      ram_check(0x30100000, 0x31000000);
 342 #endif
 343 #if 0
 344         ram_check(0x00000000, 0x02000000);
 345 #endif
 346
 347 #if 0
 348         while(1) {
 349                 hlt();
 350         }
 351 #endif
 352 }
 353