src/mainboard/dell/s1850/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include <console/console.h>
   9 #include "southbridge/intel/i82801ex/early_smbus.c"
  10 #include "northbridge/intel/e7520/raminit.h"
  11 #include "superio/nsc/pc8374/early_init.c"
  12 #include "cpu/x86/lapic/boot_cpu.c"
  13 #include "cpu/x86/mtrr/earlymtrr.c"
  14 #include "debug.c"
  15 #include "watchdog.c"
  16 // Remove comment if resets in this file are actually used.
  17 // #include "reset.c"
  18 #include "s1850_fixups.c"
  19 #include "northbridge/intel/e7520/memory_initialized.c"
  20 #include "cpu/x86/bist.h"
  21 #include <spd.h>
  22
  23 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC8374_SP1)
  24
  25 #define DEVPRES_CONFIG  ( \
  26         DEVPRES_D0F0 | \
  27         DEVPRES_D1F0 | \
  28         DEVPRES_D2F0 | \
  29         DEVPRES_D3F0 | \
  30         DEVPRES_D4F0 | \
  31         DEVPRES_D6F0 | \
  32         0 )
  33 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  34
  35 static inline int spd_read_byte(unsigned device, unsigned address)
  36 {
  37         return smbus_read_byte(device, address);
  38 }
  39
  40 #include "northbridge/intel/e7520/raminit.c"
  41 #include "lib/generic_sdram.c"
  42
  43 /* IPMI garbage. This is all test stuff, if it really works we'll move it somewhere
  44  */
  45
  46 #define nftransport  0xc
  47
  48 #define OBF  0
  49 #define IBF 1
  50
  51 #define ipmidata  0xca0
  52 #define ipmicsr  0xca4
  53
  54 static inline void  ibfzero(void)
  55 {
  56         while(inb(ipmicsr) &  (1<<IBF))
  57                 ;
  58 }
  59 static inline void  clearobf(void)
  60 {
  61         (void) inb(ipmidata);
  62 }
  63
  64 static inline void  waitobf(void)
  65 {
  66         while((inb(ipmicsr) &  (1<<OBF)) == 0)
  67                 ;
  68 }
  69
  70 /* quite possibly the stupidest interface ever designed. */
  71 static inline void  first_cmd_byte(unsigned char byte)
  72 {
  73         ibfzero();
  74         clearobf();
  75         outb(0x61, ipmicsr);
  76         ibfzero();
  77         clearobf();
  78         outb(byte, ipmidata);
  79 }
  80
  81 static inline void  next_cmd_byte(unsigned char byte)
  82 {
  83
  84         ibfzero();
  85         clearobf();
  86         outb(byte, ipmidata);
  87 }
  88
  89 static inline void  last_cmd_byte(unsigned char byte)
  90 {
  91         outb(0x62, ipmicsr);
  92
  93         ibfzero();
  94         clearobf();
  95         outb(byte,  ipmidata);
  96 }
  97
  98 static inline void read_response_byte(void)
  99 {
 100         int val = -1;
 101         if ((inb(ipmicsr)>>6) != 1)
 102                 return;
 103
 104         ibfzero();
 105         waitobf();
 106         val = inb(ipmidata);
 107         outb(0x68, ipmidata);
 108
 109         /* see if it is done */
 110         if ((inb(ipmicsr)>>6) != 1){
 111                 /* wait for the dummy read. Which describes this protocol */
 112                 waitobf();
 113                 (void)inb(ipmidata);
 114         }
 115 }
 116
 117 static inline void ipmidelay(void)
 118 {
 119         int i;
 120         for(i = 0; i < 1000; i++) {
 121                 inb(0x80);
 122         }
 123 }
 124
 125 static inline void bmc_foad(void)
 126 {
 127         unsigned char c;
 128         /* be safe; make sure it is really ready */
 129         while ((inb(ipmicsr)>>6)) {
 130                 outb(0x60, ipmicsr);
 131                 inb(ipmidata);
 132         }
 133         first_cmd_byte(nftransport << 2);
 134         ipmidelay();
 135         next_cmd_byte(0x12);
 136         ipmidelay();
 137         next_cmd_byte(2);
 138         ipmidelay();
 139         last_cmd_byte(3);
 140         ipmidelay();
 141 }
 142
 143 /* end IPMI garbage */
 144
 145 #include "arch/x86/lib/stages.c"
 146
 147 static void main(unsigned long bist)
 148 {
 149         u8 b;
 150         u16 w;
 151         u32 l;
 152         int do_reset;
 153
 154         static const struct mem_controller mch[] = {
 155                 {
 156                         .node_id = 0,
 157                         /* the wiring on this part is really messed up */
 158                         /* this is my best guess so far */
 159                         .channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, },
 160                         .channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, },
 161                 }
 162         };
 163
 164         /* superio setup */
 165         /* observed from serialice */
 166         static const u8 earlyinit[] = {
 167                 0x21, 0x11, 0x11,
 168                 0x22, 1, 1,
 169                 0x23, 05, 05,
 170                 0x24, 0x81, 0x81,
 171                 0x26, 0, 0,
 172                 0,
 173         };
 174
 175         /* using SerialICE, we've seen this basic reset sequence on the dell.
 176          * we don't understand it as it uses undocumented registers, but
 177          * we're going to clone it.
 178          */
 179         /* enable a hidden device. */
 180         b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
 181         b |= 0x8;
 182         pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
 183
 184         /* read-write lock in CMOS on LPC bridge on ICH5 */
 185         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, 4);
 186
 187         /* operate on undocumented device */
 188         l = pci_read_config32(PCI_DEV(0, 0, 2), 0xa4);
 189         l |= 0x1000;
 190         pci_write_config32(PCI_DEV(0, 0, 2), 0xa4, l);
 191
 192         l = pci_read_config32(PCI_DEV(0, 0, 2), 0x9c);
 193         l |= 0x8000;
 194         pci_write_config32(PCI_DEV(0, 0, 2), 0x9c, l);
 195
 196         /* disable undocumented device */
 197         b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
 198         b &= ~0x8;
 199         pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
 200
 201         /* set up LPC bridge bits, some of which reply on undocumented
 202          * registers
 203          */
 204
 205         b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd8);
 206         b |= 4;
 207         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, b);
 208
 209         b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd4);
 210         b |= 2;
 211         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, b);
 212
 213         /* ACPI base address */
 214         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x40, 0x800);
 215
 216         /* Enable specific ACPI features */
 217         b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0x44);
 218         b |= 0x10;
 219         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, b);
 220
 221         /* ACPI control */
 222         w = inw(0x868);
 223         outw(w|0x800, 0x868);
 224         w = inw(0x866);
 225         outw(w|2, 0x866);
 226
 227 #if 0
 228         /*seriaice shows
 229         dell does this so leave it here so I don't forget
 230          */
 231         /* SMBUS */
 232         pci_write_config16(PCI_DEV(0, 0x1f, 3), 0x20, 0x08c0);
 233
 234         /* unknown */
 235         b = inb(0x8c2);
 236         outb(0xdf, 0x8c2);
 237 #endif
 238
 239         /* another device enable? */
 240         b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
 241         b |= 2;
 242         pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
 243
 244         /* ?? */
 245         l = pci_read_config32(PCI_DEV(0, 8, 0), 0xc0);
 246         do_reset = l & 0x8000000;
 247         l |= 0x8000000;
 248         pci_write_config32(PCI_DEV(0, 8, 0), 0xc0, l);
 249
 250         if (! do_reset) {
 251                 outb(2, 0xcf9);
 252                 outb(6, 0xcf9);
 253         }
 254         if (bist == 0) {
 255                 /* Skip this if there was a built in self test failure */
 256                 early_mtrr_init();
 257                 if (memory_initialized())
 258                         skip_romstage();
 259         }
 260         /* Setup the console */
 261         mainboard_set_ich5();
 262         //bmc_foad();
 263         pc8374_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
 264         uart_init();
 265         console_init();
 266
 267         /* stuff we seem to need */
 268         pc8374_enable_dev(PNP_DEV(0x2e, PC8374_KBCK), 0);
 269
 270         /* GPIOs */
 271         pc8374_enable_dev(PNP_DEV(0x2e, PC8374_GPIO), 0xc20);
 272
 273         /* keep this in mind.
 274         SerialICE-hlp: outb 002e <= 23
 275         SerialICE-hlp:  inb 002f => 05
 276         SerialICE-hlp: outb 002f <= 05
 277         SerialICE-hlp: outb 002e <= 24
 278         SerialICE-hlp:  inb 002f => c1
 279         SerialICE-hlp: outb 002f <= c1
 280          */
 281
 282         /* Halt if there was a built in self test failure */
 283 //      report_bist_failure(bist);
 284
 285         /* MOVE ME TO A BETTER LOCATION !!! */
 286         /* config LPC decode for flash memory access */
 287         device_t dev;
 288         dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
 289         if (dev == PCI_DEV_INVALID) {
 290                 die("Missing ich5?");
 291         }
 292         pci_write_config32(dev, 0xe8, 0x00000000);
 293         pci_write_config8(dev, 0xf0, 0x00);
 294
 295 #if 0
 296         display_cpuid_update_microcode();
 297 #endif
 298 #if 1
 299         print_pci_devices();
 300 #endif
 301 #if 1
 302         enable_smbus();
 303 #endif
 304 #if 0
 305 //      dump_spd_registers(&cpu[0]);
 306         int i;
 307         for(i = 0; i < 1; i++)
 308                 dump_spd_registers();
 309 #endif
 310 #if 1
 311         show_dram_slots();
 312 #endif
 313         disable_watchdogs();
 314 //      dump_ipmi_registers();
 315         mainboard_set_e7520_leds();
 316
 317         sdram_initialize(ARRAY_SIZE(mch), mch);
 318 #if 0
 319         dump_pci_devices();
 320 #endif
 321 #if 1
 322         dump_pci_device(PCI_DEV(0, 0x00, 0));
 323 //      dump_bar14(PCI_DEV(0, 0x00, 0));
 324 #endif
 325 }