src/mainboard/dell/s1850/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include "option_table.h"
   9 #include "pc80/mc146818rtc_early.c"
  10 #include "pc80/serial.c"
  11 #include "console/console.c"
  12 #include "lib/ramtest.c"
  13 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
  14 #include "northbridge/intel/e7520/raminit.h"
  15 #include "superio/nsc/pc8374/pc8374_early_init.c"
  16 #include "cpu/x86/lapic/boot_cpu.c"
  17 #include "cpu/x86/mtrr/earlymtrr.c"
  18 #include "debug.c"
  19 #include "watchdog.c"
  20 // Remove comment if resets in this file are actually used.
  21 // #include "reset.c"
  22 #include "s1850_fixups.c"
  23 #include "northbridge/intel/e7520/memory_initialized.c"
  24 #include "cpu/x86/bist.h"
  25
  26 #define SIO_GPIO_BASE 0x680
  27 #define SIO_XBUS_BASE 0x4880
  28
  29 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC8374_SP1)
  30
  31 #define DEVPRES_CONFIG  ( \
  32         DEVPRES_D0F0 | \
  33         DEVPRES_D1F0 | \
  34         DEVPRES_D2F0 | \
  35         DEVPRES_D3F0 | \
  36         DEVPRES_D4F0 | \
  37         DEVPRES_D6F0 | \
  38         0 )
  39 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  40
  41 #define RECVENA_CONFIG  0x0808090a
  42 #define RECVENB_CONFIG  0x0808090a
  43
  44 static inline int spd_read_byte(unsigned device, unsigned address)
  45 {
  46         return smbus_read_byte(device, address);
  47 }
  48
  49 /* this is very highly mainboard dependent, related to wiring */
  50 /* from factory BIOS via lspci */
  51 #define DIMM_MAP_LOGICAL 0x2841
  52 #include "northbridge/intel/e7520/raminit.c"
  53 #include "lib/generic_sdram.c"
  54
  55 /* IPMI garbage. This is all test stuff, if it really works we'll move it somewhere
  56  */
  57
  58 #define nftransport  0xc
  59
  60 #define OBF  0
  61 #define IBF 1
  62
  63 #define ipmidata  0xca0
  64 #define ipmicsr  0xca4
  65
  66 static inline void  ibfzero(void)
  67 {
  68         while(inb(ipmicsr) &  (1<<IBF))
  69                 ;
  70 }
  71 static inline void  clearobf(void)
  72 {
  73         (void) inb(ipmidata);
  74 }
  75
  76 static inline void  waitobf(void)
  77 {
  78         while((inb(ipmicsr) &  (1<<OBF)) == 0)
  79                 ;
  80 }
  81 /* quite possibly the stupidest interface ever designed. */
  82 static inline void  first_cmd_byte(unsigned char byte)
  83 {
  84         ibfzero();
  85         clearobf();
  86         outb(0x61, ipmicsr);
  87         ibfzero();
  88         clearobf();
  89         outb(byte, ipmidata);
  90 }
  91
  92 static inline void  next_cmd_byte(unsigned char byte)
  93 {
  94
  95         ibfzero();
  96         clearobf();
  97         outb(byte, ipmidata);
  98 }
  99
 100 static inline void  last_cmd_byte(unsigned char byte)
 101 {
 102         outb(0x62, ipmicsr);
 103
 104         ibfzero();
 105         clearobf();
 106         outb(byte,  ipmidata);
 107 }
 108
 109 static inline void read_response_byte(void)
 110 {
 111         int val = -1;
 112         if ((inb(ipmicsr)>>6) != 1)
 113                 return;
 114
 115         ibfzero();
 116         waitobf();
 117         val = inb(ipmidata);
 118         outb(0x68, ipmidata);
 119
 120         /* see if it is done */
 121         if ((inb(ipmicsr)>>6) != 1){
 122                 /* wait for the dummy read. Which describes this protocol */
 123                 waitobf();
 124                 (void)inb(ipmidata);
 125         }
 126 }
 127
 128 static inline void ipmidelay(void)
 129 {
 130         int i;
 131         for(i = 0; i < 1000; i++) {
 132                 inb(0x80);
 133         }
 134 }
 135
 136 static inline void bmc_foad(void)
 137 {
 138         unsigned char c;
 139         /* be safe; make sure it is really ready */
 140         while ((inb(ipmicsr)>>6)) {
 141                 outb(0x60, ipmicsr);
 142                 inb(ipmidata);
 143         }
 144         first_cmd_byte(nftransport << 2);
 145         ipmidelay();
 146         next_cmd_byte(0x12);
 147         ipmidelay();
 148         next_cmd_byte(2);
 149         ipmidelay();
 150         last_cmd_byte(3);
 151         ipmidelay();
 152 }
 153
 154 /* end IPMI garbage */
 155
 156 #include "arch/i386/lib/stages.c"
 157
 158 static void main(unsigned long bist)
 159 {
 160         u8 b;
 161         u16 w;
 162         u32 l;
 163         int do_reset;
 164         /*
 165          *
 166          *
 167          */
 168         static const struct mem_controller mch[] = {
 169                 {
 170                         .node_id = 0,
 171                         /*
 172                         .f0 = PCI_DEV(0, 0x00, 0),
 173                         .f1 = PCI_DEV(0, 0x00, 1),
 174                         .f2 = PCI_DEV(0, 0x00, 2),
 175                         .f3 = PCI_DEV(0, 0x00, 3),
 176                         */
 177                         /* the wiring on this part is really messed up */
 178                         /* this is my best guess so far */
 179                         .channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, },
 180                         .channel1 = {(0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, (0xa<<3)|7, },
 181                 }
 182         };
 183
 184         /* superio setup */
 185         /* observed from serialice */
 186         static const u8 earlyinit[] = {
 187                 0x21, 0x11, 0x11,
 188                 0x22, 1, 1,
 189                 0x23, 05, 05,
 190                 0x24, 0x81, 0x81,
 191                 0x26, 0, 0,
 192                 0,
 193         };
 194
 195         /* using SerialICE, we've seen this basic reset sequence on the dell.
 196          * we don't understand it as it uses undocumented registers, but
 197          * we're going to clone it.
 198          */
 199         /* enable a hidden device. */
 200         b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
 201         b |= 0x8;
 202         pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
 203
 204         /* read-write lock in CMOS on LPC bridge on ICH5 */
 205         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, 4);
 206
 207         /* operate on undocumented device */
 208         l = pci_read_config32(PCI_DEV(0, 0, 2), 0xa4);
 209         l |= 0x1000;
 210         pci_write_config32(PCI_DEV(0, 0, 2), 0xa4, l);
 211
 212         l = pci_read_config32(PCI_DEV(0, 0, 2), 0x9c);
 213         l |= 0x8000;
 214         pci_write_config32(PCI_DEV(0, 0, 2), 0x9c, l);
 215
 216         /* disable undocumented device */
 217         b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
 218         b &= ~0x8;
 219         pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
 220
 221         /* set up LPC bridge bits, some of which reply on undocumented
 222          * registers
 223          */
 224
 225         b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd8);
 226         b |= 4;
 227         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd8, b);
 228
 229         b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xd4);
 230         b |= 2;
 231         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, b);
 232
 233         /* ACPI base address */
 234         pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x40, 0x800);
 235
 236         /* Enable specific ACPI features */
 237         b= pci_read_config8(PCI_DEV(0, 0x1f, 0), 0x44);
 238         b |= 0x10;
 239         pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, b);
 240
 241         /* ACPI control */
 242         w = inw(0x868);
 243         outw(w|0x800, 0x868);
 244         w = inw(0x866);
 245         outw(w|2, 0x866);
 246
 247 #if 0
 248         /*seriaice shows
 249         dell does this so leave it here so I don't forget
 250          */
 251         /* SMBUS */
 252         pci_write_config16(PCI_DEV(0, 0x1f, 3), 0x20, 0x08c0);
 253
 254         /* unknown */
 255         b = inb(0x8c2);
 256         outb(0xdf, 0x8c2);
 257 #endif
 258
 259         /* another device enable? */
 260         b = pci_read_config8(PCI_DEV(0, 0, 0), 0xf4);
 261         b |= 2;
 262         pci_write_config8(PCI_DEV(0, 0, 0), 0xf4, b);
 263
 264         /* ?? */
 265         l = pci_read_config32(PCI_DEV(0, 8, 0), 0xc0);
 266         do_reset = l & 0x8000000;
 267         l |= 0x8000000;
 268         pci_write_config32(PCI_DEV(0, 8, 0), 0xc0, l);
 269
 270         if (! do_reset) {
 271                 outb(2, 0xcf9);
 272                 outb(6, 0xcf9);
 273         }
 274         if (bist == 0) {
 275                 /* Skip this if there was a built in self test failure */
 276                 early_mtrr_init();
 277                 if (memory_initialized()) {
 278                         skip_romstage();
 279                 }
 280         }
 281         /* Setup the console */
 282         mainboard_set_ich5();
 283         //bmc_foad();
 284         pc8374_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
 285         uart_init();
 286         console_init();
 287
 288         /* stuff we seem to need */
 289         pc8374_enable_dev(PNP_DEV(0x2e, PC8374_KBCK), 0);
 290
 291         /* GPIOs */
 292         pc8374_enable_dev(PNP_DEV(0x2e, PC8374_GPIO), 0xc20);
 293
 294         /* keep this in mind.
 295         SerialICE-hlp: outb 002e <= 23
 296         SerialICE-hlp:  inb 002f => 05
 297         SerialICE-hlp: outb 002f <= 05
 298         SerialICE-hlp: outb 002e <= 24
 299         SerialICE-hlp:  inb 002f => c1
 300         SerialICE-hlp: outb 002f <= c1
 301          */
 302
 303         /* Halt if there was a built in self test failure */
 304 //      report_bist_failure(bist);
 305
 306         /* MOVE ME TO A BETTER LOCATION !!! */
 307         /* config LPC decode for flash memory access */
 308         device_t dev;
 309         dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
 310         if (dev == PCI_DEV_INVALID) {
 311                 die("Missing ich5?");
 312         }
 313         pci_write_config32(dev, 0xe8, 0x00000000);
 314         pci_write_config8(dev, 0xf0, 0x00);
 315
 316 #if 0
 317         display_cpuid_update_microcode();
 318 #endif
 319 #if 1
 320         print_pci_devices();
 321 #endif
 322 #if 1
 323         enable_smbus();
 324 #endif
 325 #if 0
 326 //      dump_spd_registers(&cpu[0]);
 327         int i;
 328         for(i = 0; i < 1; i++) {
 329                 dump_spd_registers();
 330         }
 331 #endif
 332 #if 1
 333         show_dram_slots();
 334 #endif
 335         disable_watchdogs();
 336 //      dump_ipmi_registers();
 337         mainboard_set_e7520_leds();
 338
 339         sdram_initialize(ARRAY_SIZE(mch), mch);
 340 #if 0
 341         dump_pci_devices();
 342 #endif
 343 #if 1
 344         dump_pci_device(PCI_DEV(0, 0x00, 0));
 345 //      dump_bar14(PCI_DEV(0, 0x00, 0));
 346 #endif
 347
 348 #if 1 // temporarily disabled
 349         /* Check the first 1M */
 350 //      ram_check(0x00000000, 0x000100000);
 351 //      ram_check(0x00000000, 0x000a0000);
 352 //      ram_check(0x00100000, 0x01000000);
 353         ram_check(0x00100000, 0x00100100);
 354         /* check the first 1M in the 3rd Gig */
 355 //      ram_check(0x30100000, 0x31000000);
 356 #endif
 357 #if 0
 358         ram_check(0x00000000, 0x02000000);
 359 #endif
 360
 361 #if 0
 362         while(1) {
 363                 hlt();
 364         }
 365 #endif
 366 }
 367