src/mainboard/dell/s1850/mptable.c

   1 #include <console/console.h>
   2 #include <arch/smp/mpspec.h>
   3 #include <arch/ioapic.h>
   4 #include <device/pci.h>
   5 #include <string.h>
   6 #include <stdint.h>
   7
   8 static void *smp_write_config_table(void *v)
   9 {
  10         struct mp_config_table *mc;
  11         int bus_isa;
  12         unsigned char bus_pxhd_1;
  13         unsigned char bus_pxhd_2;
  14         unsigned char bus_pxhd_3;
  15         unsigned char bus_pxhd_4;
  16         unsigned char bus_ich5r_1;
  17
  18         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  19
  20         mptable_init(mc, LAPIC_ADDR);
  21
  22         smp_write_processors(mc);
  23
  24         {
  25                 device_t dev;
  26
  27                 /* ich5r */
  28                 dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
  29                 if (dev) {
  30                         bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  31                 }
  32                 else {
  33                         printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
  34                         bus_ich5r_1 = 7;
  35                 }
  36                 /* pxhd-1 */
  37                 dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
  38                 if (dev) {
  39                         bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  40                 }
  41                 else {
  42                         printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.0, using defaults\n");
  43                         bus_pxhd_1 = 2;
  44                 }
  45                 /* pxhd-2 */
  46                 dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
  47                 if (dev) {
  48                         bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  49                 }
  50                 else {
  51                         printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.2, using defaults\n");
  52                         bus_pxhd_2 = 3;
  53                 }
  54
  55                 /* pxhd-3 */
  56                 dev = dev_find_slot(0, PCI_DEVFN(0x4,0));
  57                 if (dev) {
  58                         bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  59                 }
  60                 else {
  61                         printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0, using defaults\n");
  62                         bus_pxhd_3 = 5;
  63                 }
  64                 /* pxhd-4 */
  65                 dev = dev_find_slot(0, PCI_DEVFN(0x06,0));
  66                 if (dev) {
  67                         bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  68                 }
  69                 else {
  70                         printk(BIOS_DEBUG, "ERROR - could not find PCI 0:06.0, using defaults\n");
  71                         bus_pxhd_4 = 6;
  72                 }
  73
  74         }
  75
  76         mptable_write_buses(mc, NULL, &bus_isa);
  77
  78         /* IOAPIC handling */
  79
  80         smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
  81         {
  82                 struct resource *res;
  83                 device_t dev;
  84                 /* pxhd apic 3 */
  85                 dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
  86                 if (dev) {
  87                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  88                         if (res) {
  89                                 smp_write_ioapic(mc, 0x03, 0x20, res->base);
  90                         }
  91                 }
  92                 else {
  93                         printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
  94                 }
  95                 /* pxhd apic 4 */
  96                 dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
  97                 if (dev) {
  98                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
  99                         if (res) {
 100                                 smp_write_ioapic(mc, 0x04, 0x20, res->base);
 101                         }
 102                 }
 103                 else {
 104                         printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
 105                 }
 106         }
 107
 108         mptable_add_isa_interrupts(mc, bus_isa, 0x2, 0);
 109
 110         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 111                 0x00, 0x74, 0x02, 0x10);
 112         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 113                 0x00, 0x76, 0x02, 0x12);
 114         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 115                 0x00, 0x77, 0x02, 0x17);
 116         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 117                 0x00, 0x75, 0x02, 0x13);
 118         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 119                 0x00, 0x74, 0x02, 0x10);
 120         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 121                 0x00, 0x7c, 0x02, 0x12);
 122         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 123                 0x00, 0x7d, 0x02, 0x11);
 124         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 125                 bus_pxhd_1, 0x08, 0x03, 0x00);
 126         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 127                 bus_pxhd_1, 0x0c, 0x03, 0x06);
 128         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 129                 bus_pxhd_1, 0x0d, 0x03, 0x07);
 130         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 131                 bus_pxhd_2, 0x08, 0x04, 0x00);
 132         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 133                 bus_ich5r_1, 0x04, 0x02, 0x10);
 134         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 135                 bus_pxhd_4, 0x00, 0x02, 0x10);
 136 #if 0
 137         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 138                 (bus_isa - 1), 0x04, 0x02, 0x10);
 139 #endif
 140         /* Standard local interrupt assignments */
 141 #if 0
 142         smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 143                 bus_isa, 0x00, MP_APIC_ALL, 0x00);
 144 #endif
 145         smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 146                 bus_isa, 0x00, MP_APIC_ALL, 0x01);
 147
 148         /* There is no extension information... */
 149
 150         /* Compute the checksums */
 151         return mptable_finalize(mc);
 152 }
 153
 154 unsigned long write_smp_table(unsigned long addr)
 155 {
 156         void *v;
 157         v = smp_write_floating_table(addr, 0);
 158         return (unsigned long)smp_write_config_table(v);
 159 }
 160