src/mainboard/dell/s1850/mptable.c

   1 #include <console/console.h>
   2 #include <arch/smp/mpspec.h>
   3 #include <device/pci.h>
   4 #include <string.h>
   5 #include <stdint.h>
   6
   7 static void *smp_write_config_table(void *v)
   8 {
   9         static const char sig[4] = "PCMP";
  10         static const char oem[8] = "COREBOOT";
  11         static const char productid[12] = "S2850       ";
  12         struct mp_config_table *mc;
  13         unsigned char bus_num;
  14         unsigned char bus_isa;
  15         unsigned char bus_pxhd_1;
  16         unsigned char bus_pxhd_2;
  17         unsigned char bus_pxhd_3;
  18         unsigned char bus_pxhd_4;
  19         unsigned char bus_ich5r_1;
  20
  21         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  22         memset(mc, 0, sizeof(*mc));
  23
  24         memcpy(mc->mpc_signature, sig, sizeof(sig));
  25         mc->mpc_length = sizeof(*mc); /* initially just the header */
  26         mc->mpc_spec = 0x04;
  27         mc->mpc_checksum = 0; /* not yet computed */
  28         memcpy(mc->mpc_oem, oem, sizeof(oem));
  29         memcpy(mc->mpc_productid, productid, sizeof(productid));
  30         mc->mpc_oemptr = 0;
  31         mc->mpc_oemsize = 0;
  32         mc->mpc_entry_count = 0; /* No entries yet... */
  33         mc->mpc_lapic = LAPIC_ADDR;
  34         mc->mpe_length = 0;
  35         mc->mpe_checksum = 0;
  36         mc->reserved = 0;
  37
  38         smp_write_processors(mc);
  39
  40         {
  41                 device_t dev;
  42
  43                 /* ich5r */
  44                 dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
  45                 if (dev) {
  46                         bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  47                         bus_isa    = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
  48                         bus_isa++;
  49                 }
  50                 else {
  51                         printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
  52
  53                         bus_ich5r_1 = 7;
  54                         bus_isa = 8;
  55                 }
  56                 /* pxhd-1 */
  57                 dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
  58                 if (dev) {
  59                         bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  60
  61                 }
  62                 else {
  63                         printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.0, using defaults\n");
  64
  65                         bus_pxhd_1 = 2;
  66                 }
  67                 /* pxhd-2 */
  68                 dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
  69                 if (dev) {
  70                         bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  71
  72                 }
  73                 else {
  74                         printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.2, using defaults\n");
  75
  76                         bus_pxhd_2 = 3;
  77                 }
  78
  79                 /* pxhd-3 */
  80                 dev = dev_find_slot(0, PCI_DEVFN(0x4,0));
  81                 if (dev) {
  82                         bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  83
  84                 }
  85                 else {
  86                         printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0, using defaults\n");
  87
  88                         bus_pxhd_3 = 5;
  89                 }
  90                 /* pxhd-4 */
  91                 dev = dev_find_slot(0, PCI_DEVFN(0x06,0));
  92                 if (dev) {
  93                         bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  94
  95                 }
  96                 else {
  97                         printk(BIOS_DEBUG, "ERROR - could not find PCI 0:06.0, using defaults\n");
  98
  99                         bus_pxhd_4 = 6;
 100                 }
 101
 102         }
 103
 104         /* define bus and isa numbers */
 105         for(bus_num = 0; bus_num < bus_isa; bus_num++) {
 106                 smp_write_bus(mc, bus_num, "PCI   ");
 107         }
 108         smp_write_bus(mc, bus_isa, "ISA   ");
 109
 110         /* IOAPIC handling */
 111
 112         smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
 113         {
 114                 struct resource *res;
 115                 device_t dev;
 116                 /* pxhd apic 3 */
 117                 dev = dev_find_slot(1, PCI_DEVFN(0x00,1));
 118                 if (dev) {
 119                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
 120                         if (res) {
 121                                 smp_write_ioapic(mc, 0x03, 0x20, res->base);
 122                         }
 123                 }
 124                 else {
 125                         printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n");
 126                 }
 127                 /* pxhd apic 4 */
 128                 dev = dev_find_slot(1, PCI_DEVFN(0x00,3));
 129                 if (dev) {
 130                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
 131                         if (res) {
 132                                 smp_write_ioapic(mc, 0x04, 0x20, res->base);
 133                         }
 134                 }
 135                 else {
 136                         printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n");
 137                 }
 138         }
 139         /* ISA backward compatibility interrupts  */
 140         smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 141                 bus_isa, 0x00, 0x02, 0x00);
 142         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 143                 bus_isa, 0x01, 0x02, 0x01);
 144         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 145                 bus_isa, 0x00, 0x02, 0x02);
 146         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 147                 bus_isa, 0x03, 0x02, 0x03);
 148         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 149                 bus_isa, 0x04, 0x02, 0x04);
 150         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 151                 0x00, 0x74, 0x02, 0x10);
 152         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 153                 bus_isa, 0x06, 0x02, 0x06);
 154         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 155                 0x00, 0x76, 0x02, 0x12);
 156         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 157                 bus_isa, 0x08, 0x02, 0x08);
 158         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 159                 bus_isa, 0x09, 0x02, 0x09);
 160         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 161                 0x00, 0x77, 0x02, 0x17);
 162         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 163                 0x00, 0x75, 0x02, 0x13);
 164         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 165                 bus_isa, 0x0c, 0x02, 0x0c);
 166         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 167                 bus_isa, 0x0d, 0x02, 0x0d);
 168         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 169                 bus_isa, 0x0e, 0x02, 0x0e);
 170         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 171                 bus_isa, 0x0f, 0x02, 0x0f);
 172         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 173                 0x00, 0x74, 0x02, 0x10);
 174         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 175                 0x00, 0x7c, 0x02, 0x12);
 176         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 177                 0x00, 0x7d, 0x02, 0x11);
 178         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 179                 bus_pxhd_1, 0x08, 0x03, 0x00);
 180         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 181                 bus_pxhd_1, 0x0c, 0x03, 0x06);
 182         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 183                 bus_pxhd_1, 0x0d, 0x03, 0x07);
 184         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 185                 bus_pxhd_2, 0x08, 0x04, 0x00);
 186         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 187                 bus_ich5r_1, 0x04, 0x02, 0x10);
 188         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 189                 bus_pxhd_4, 0x00, 0x02, 0x10);
 190 #if 0
 191         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
 192                 (bus_isa - 1), 0x04, 0x02, 0x10);
 193 #endif
 194         /* Standard local interrupt assignments */
 195 #if 0
 196         smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 197                 bus_isa, 0x00, MP_APIC_ALL, 0x00);
 198 #endif
 199         smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,
 200                 bus_isa, 0x00, MP_APIC_ALL, 0x01);
 201
 202         /* There is no extension information... */
 203
 204         /* Compute the checksums */
 205         mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 206
 207         mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 208         printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
 209                 mc, smp_next_mpe_entry(mc));
 210         return smp_next_mpe_entry(mc);
 211 }
 212
 213 unsigned long write_smp_table(unsigned long addr)
 214 {
 215         void *v;
 216         v = smp_write_floating_table(addr);
 217         return (unsigned long)smp_write_config_table(v);
 218 }
 219