src/mainboard/broadcom/blast/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <console/console.h>
  10 #include <cpu/amd/model_fxx_rev.h>
  11 #include "northbridge/amd/amdk8/incoherent_ht.c"
  12 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
  13 #include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
  14 #include "northbridge/amd/amdk8/raminit.h"
  15 #include "cpu/amd/model_fxx/apic_timer.c"
  16 #include "lib/delay.c"
  17 #include "cpu/x86/lapic/boot_cpu.c"
  18 #include "northbridge/amd/amdk8/reset_test.c"
  19 #include "northbridge/amd/amdk8/debug.c"
  20 #include "superio/nsc/pc87417/pc87417_early_serial.c"
  21 #include "cpu/x86/mtrr/earlymtrr.c"
  22 #include "cpu/x86/bist.h"
  23 #include "northbridge/amd/amdk8/setup_resource_map.c"
  24 #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
  25
  26 #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
  27 #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
  28
  29 static void memreset_setup(void)
  30 {
  31 }
  32
  33 static void memreset(int controllers, const struct mem_controller *ctrl)
  34 {
  35 }
  36
  37 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  38 {
  39 #define SMBUS_HUB 0x71
  40         unsigned device=(ctrl->channel0[0])>>8;
  41         smbus_send_byte(SMBUS_HUB, device);
  42 }
  43
  44 #if 0
  45 static inline void change_i2c_mux(unsigned device)
  46 {
  47 #define SMBUS_HUB 0x71
  48         int ret;
  49         print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
  50         ret = smbus_send_byte(SMBUS_HUB, device);
  51         print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n");
  52 }
  53 #endif
  54
  55 static inline int spd_read_byte(unsigned device, unsigned address)
  56 {
  57         return smbus_read_byte(device, address);
  58 }
  59
  60 #include "northbridge/amd/amdk8/raminit.c"
  61 #include "northbridge/amd/amdk8/coherent_ht.c"
  62 #include "lib/generic_sdram.c"
  63 #include "resourcemap.c" /* tyan does not want the default */
  64 #include "cpu/amd/dualcore/dualcore.c"
  65 #include <spd.h>
  66 #include "cpu/amd/car/post_cache_as_ram.c"
  67 #include "cpu/amd/model_fxx/init_cpus.c"
  68 #include "northbridge/amd/amdk8/early_ht.c"
  69
  70 #define RC0 (6<<8)
  71 #define RC1 (7<<8)
  72
  73 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  74 {
  75         static const uint16_t spd_addr[] = {
  76                 RC0|DIMM0, RC0|DIMM2, 0, 0,
  77                 RC0|DIMM1, RC0|DIMM3, 0, 0,
  78                 RC1|DIMM0, RC1|DIMM2, 0, 0,
  79                 RC1|DIMM1, RC1|DIMM3, 0, 0,
  80         };
  81
  82         int needs_reset;
  83         unsigned bsp_apicid = 0;
  84
  85         struct mem_controller ctrl[8];
  86         unsigned nodes;
  87
  88         if (!cpu_init_detectedx && boot_cpu()) {
  89                 /* Nothing special needs to be done to find bus 0 */
  90                 /* Allow the HT devices to be found */
  91
  92                 enumerate_ht_chain();
  93
  94                 bcm5785_enable_rom();
  95
  96                 bcm5785_enable_lpc();
  97
  98                 //enable RTC
  99                 pc87417_enable_dev(RTC_DEV);
 100         }
 101
 102         if (bist == 0) {
 103                 bsp_apicid = init_cpus(cpu_init_detectedx);
 104         }
 105 //      post_code(0x32);
 106
 107         pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 108 //      post_code(0x33);
 109
 110         uart_init();
 111 //      post_code(0x34);
 112
 113         console_init();
 114
 115         /* Halt if there was a built in self test failure */
 116         report_bist_failure(bist);
 117
 118         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 119
 120         setup_blast_resource_map();
 121
 122 #if 0
 123         dump_pci_device(PCI_DEV(0, 0x18, 0));
 124         dump_pci_device(PCI_DEV(0, 0x19, 0));
 125 #endif
 126
 127         needs_reset = setup_coherent_ht_domain();
 128
 129 #if CONFIG_LOGICAL_CPUS==1
 130         // It is said that we should start core1 after all core0 launched
 131         wait_all_core0_started();
 132         start_other_cores();
 133 #endif
 134         wait_all_aps_started(bsp_apicid);
 135
 136         needs_reset |= ht_setup_chains_x();
 137
 138         bcm5785_early_setup();
 139
 140         if (needs_reset) {
 141                 print_info("ht reset -\n");
 142                 soft_reset();
 143         }
 144
 145         allow_all_aps_stop(bsp_apicid);
 146
 147         nodes = get_nodes();
 148         //It's the time to set ctrl now;
 149         fill_mem_ctrl(nodes, ctrl, spd_addr);
 150
 151         enable_smbus();
 152
 153 #if 0
 154         int i;
 155         for(i=4;i<8;i++) {
 156                 change_i2c_mux(i);
 157                 dump_smbus_registers();
 158         }
 159 #endif
 160
 161         memreset_setup();
 162
 163 //      init_timer();
 164
 165         sdram_initialize(nodes, ctrl);
 166
 167 #if 0
 168         print_pci_devices();
 169 #endif
 170
 171 #if 0
 172         dump_pci_devices();
 173 #endif
 174
 175         post_cache_as_ram();
 176 }