3 #include <device/pci_def.h>
5 #include <device/pnp_def.h>
6 #include <arch/romcc_io.h>
7 #include <cpu/x86/lapic.h>
8 #include <pc80/mc146818rtc.h>
9 #include <console/console.h>
10 #include <cpu/amd/model_fxx_rev.h>
11 #include "northbridge/amd/amdk8/incoherent_ht.c"
12 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
13 #include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
14 #include "northbridge/amd/amdk8/raminit.h"
15 #include "cpu/amd/model_fxx/apic_timer.c"
16 #include "lib/delay.c"
17 #include "cpu/x86/lapic/boot_cpu.c"
18 #include "northbridge/amd/amdk8/reset_test.c"
19 #include "northbridge/amd/amdk8/debug.c"
20 #include "superio/nsc/pc87417/pc87417_early_serial.c"
21 #include "cpu/x86/mtrr/earlymtrr.c"
22 #include "cpu/x86/bist.h"
23 #include "northbridge/amd/amdk8/setup_resource_map.c"
24 #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
26 #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
27 #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
29 static void memreset_setup(void) { }
30 static void memreset(int controllers, const struct mem_controller *ctrl) { }
32 static inline void activate_spd_rom(const struct mem_controller *ctrl)
34 #define SMBUS_HUB 0x71
35 unsigned device=(ctrl->channel0[0])>>8;
36 smbus_send_byte(SMBUS_HUB, device);
40 static inline void change_i2c_mux(unsigned device)
42 #define SMBUS_HUB 0x71
44 print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
45 ret = smbus_send_byte(SMBUS_HUB, device);
46 print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n");
50 static inline int spd_read_byte(unsigned device, unsigned address)
52 return smbus_read_byte(device, address);
55 #include "northbridge/amd/amdk8/raminit.c"
56 #include "northbridge/amd/amdk8/coherent_ht.c"
57 #include "lib/generic_sdram.c"
58 #include "resourcemap.c"
59 #include "cpu/amd/dualcore/dualcore.c"
61 #include "cpu/amd/car/post_cache_as_ram.c"
62 #include "cpu/amd/model_fxx/init_cpus.c"
63 #include "northbridge/amd/amdk8/early_ht.c"
68 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
70 static const uint16_t spd_addr[] = {
71 RC0|DIMM0, RC0|DIMM2, 0, 0,
72 RC0|DIMM1, RC0|DIMM3, 0, 0,
73 RC1|DIMM0, RC1|DIMM2, 0, 0,
74 RC1|DIMM1, RC1|DIMM3, 0, 0,
78 unsigned bsp_apicid = 0, nodes;
79 struct mem_controller ctrl[8];
81 if (!cpu_init_detectedx && boot_cpu()) {
82 /* Nothing special needs to be done to find bus 0 */
83 /* Allow the HT devices to be found */
87 pc87417_enable_dev(RTC_DEV); /* Enable RTC */
91 bsp_apicid = init_cpus(cpu_init_detectedx);
93 pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
97 /* Halt if there was a built in self test failure */
98 report_bist_failure(bist);
100 print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
102 setup_blast_resource_map();
105 dump_pci_device(PCI_DEV(0, 0x18, 0));
106 dump_pci_device(PCI_DEV(0, 0x19, 0));
109 needs_reset = setup_coherent_ht_domain();
111 #if CONFIG_LOGICAL_CPUS==1
112 // It is said that we should start core1 after all core0 launched
113 wait_all_core0_started();
116 wait_all_aps_started(bsp_apicid);
118 needs_reset |= ht_setup_chains_x();
120 bcm5785_early_setup();
123 print_info("ht reset -\n");
127 allow_all_aps_stop(bsp_apicid);
130 //It's the time to set ctrl now;
131 fill_mem_ctrl(nodes, ctrl, spd_addr);
139 dump_smbus_registers();
147 sdram_initialize(nodes, ctrl);