1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
4 #include <device/pci.h>
7 #if CONFIG_LOGICAL_CPUS==1
8 #include <cpu/amd/multicore.h>
10 #include <cpu/amd/amdk8_sysconf.h>
12 extern unsigned char bus_bcm5780[7];
13 extern unsigned char bus_bcm5785_0;
14 extern unsigned char bus_bcm5785_1;
15 extern unsigned char bus_bcm5785_1_1;
16 extern unsigned apicid_bcm5785[3];
18 extern unsigned sbdn2;
20 static void *smp_write_config_table(void *v)
22 struct mp_config_table *mc;
25 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
27 mptable_init(mc, LAPIC_ADDR);
29 smp_write_processors(mc);
33 mptable_write_buses(mc, NULL, &bus_isa);
35 /*I/O APICs: APIC ID Version State Address*/
40 dev = dev_find_device(0x1166, 0x0235, dev);
42 res = find_resource(dev, PCI_BASE_ADDRESS_0);
44 smp_write_ioapic(mc, apicid_bcm5785[i], 0x11, res->base);
51 mptable_add_isa_interrupts(mc, bus_isa, apicid_bcm5785[0], 0);
54 outb(0x02, 0xc00); outb(0x0e, 0xc01);
56 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, apicid_bcm5785[0], 0xe); // IDE
59 outb(0x07, 0xc00); outb(0x0f, 0xc01);
60 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1, (0x0e<<2)|0, apicid_bcm5785[0], 0xf);
63 outb(0x01, 0xc00); outb(0x0a, 0xc01);
65 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, ((2+sysconf.sbdn)<<2)|i, apicid_bcm5785[0], 0xa); //
71 /* why here? must get the BAR and PCI command bit 1 set before enable it ....*/
74 dev = dev_find_device(0x1166, 0x0205, 0);
77 dword = pci_read_config32(dev, 0x6c);
78 dword |= (1<<4); // enable interrupts
79 pci_write_config32(dev, 0x6c, dword);
85 //First pci-x slot (on bcm5785) under bus_bcm5785_1:d.0
87 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_1_1, (4<<2)|i, apicid_bcm5785[1], 2 + (0+i)%4); //
91 //pci slot (on bcm5785)
93 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (4<<2)|i, apicid_bcm5785[1], i%2); //
98 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5785_0, (5<<2)|0, apicid_bcm5785[1], 0x1);
102 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (4<<2)|i, apicid_bcm5785[1], 6 + (0+i)%4); //
106 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[1], (5<<2)|i, apicid_bcm5785[1], 6 + (1+i)%4); //
111 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[2], (4<<2)|i, apicid_bcm5785[1], 0xa + (0+i)%4); //
117 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[5], (0<<2)|i, apicid_bcm5785[1], 0xe); //
123 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[3], (0<<2)|i, apicid_bcm5785[1], 0xc); //
129 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_bcm5780[4], (0<<2)|i, apicid_bcm5785[1], 0xd); //
132 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
133 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
134 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
135 /* There is no extension information... */
137 /* Compute the checksums */
138 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
139 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
140 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
141 mc, smp_next_mpe_entry(mc));
142 return smp_next_mpe_entry(mc);
145 unsigned long write_smp_table(unsigned long addr)
148 v = smp_write_floating_table(addr);
149 return (unsigned long)smp_write_config_table(v);